• Title/Summary/Keyword: Electronic devices

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Formation of Ohmic Contact to AlGaN/GaN Heterostructure on Sapphire

  • Kim, Zin-Sig;Ahn, Hokyun;Lim, Jong-Won;Nam, Eunsoo
    • Proceedings of the Korean Vacuum Society Conference
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    • 2014.02a
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    • pp.292-292
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    • 2014
  • Wide band gap semiconductors, such as III-nitrides (GaN, AlN, InN, and their alloys), SiC, and diamond are expected to play an important role in the next-generation electronic devices. Specifically, GaN-based high electron mobility transistors (HEMTs) have been targeted for high power, high frequency, and high temperature operation electronic devices for mobile communication systems, radars, and power electronics because of their high critical breakdown fields, high saturation velocities, and high thermal conductivities. For the stable operation, high power, high frequency and high breakdown voltage and high current density, the fabrication methods have to be optimized with considerable attention. In this study, low ohmic contact resistance and smooth surface morphology to AlGaN/GaN on 2 inch c-plane sapphire substrate has been obtained with stepwise annealing at three different temperatures. The metallization was performed under deposition of a composite metal layer of Ti/Al/Ni/Au with thickness. After multi-layer metal stacking, rapid thermal annealing (RTA) process was applied with stepwise annealing temperature program profile. As results, we obtained a minimum specific contact resistance of $1.6{\times}10^{-7}{\Omega}cm2$.

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The Properties of BST Thin Films by Thickness (두께 변화에 따른 BST 박막의 특성)

  • Hong, Kyung-Jin;Min, Yong-Ki;Cho, Jae-Cheol
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2001.11b
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    • pp.455-458
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    • 2001
  • The thin films of high pemitivity in ferroelectric materials using a capacitor are applied to DRAMs and FRAMs. (Ba, Sr)$TiO_3$ thin films as ferroelectric materials were prepared by the sol-gel method and made by spin-coating on the Pt/Ti/$SiO_2/Si$ substrate at 4,000 [rpm] for 10 seconds. The devices of BST thin films to composite $(Ba_{0.7},Sr_{0.3})TiO_3$ were fabricated by changing of the depositing layer number on $Pt/Ti/SiO_2/Si$ substrate. The thin film capacitor to be ferroelectric devices was investigated by structural and electrical properties. The thickness of BST thin films at each coating numbers 3, 4 and 5 times was $2500[\AA]$, $3500[\AA]$, $3800[\AA]$. The dielectric factor of thin film when the coating numbers were 3, 4 and 5 times was 190, 400 and 460 on frequency l[MHz]. The dielectric loss of BST thin film was linearly increased by increasing of the specimen area.

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K-band Coplanar Stripline Resonator for Microwave Tunable Devices (마이크로파 가변 소자용 K-band Coplanar Stripline 공진기 설계)

  • Kang, Chong-Yun;Yoon, Seok-Jin;Kim, Hyun-Jai
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.18 no.6
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    • pp.532-537
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    • 2005
  • In order to develop a tunable resonator which can be easily operated by DC bias and applied for microwave tunable filters and devices using ferroelectric thin or thick films, the non conductor backed-and conductor backed- coplanar stripline resonators have been designed and analyzed. They have been designed to be operated at 25 GHz which involve coplanar stripline input and output ports. The resonators have been simulated and analyzed using Ansoft HFSS. The research has been focused on the Quality factor of the coplanar stripline resonator. The conductor Q, box Q, and radiation Q of the resonators have been analyzed and calculated according to the substrate thickness & conductor width of the resonators. From these parameters, the loss factors of the coplanar stripline resonator have been investigated. The conducting Q of the coplanar stripline resonator has no relation with the thickness of dielectric substrate and increases as the conductor width increases. The box Q has no much relation with the thickness of substrate and the conductor width, which is above 2000. The radiation loss increases as the thickness of substrate and the conductor width increase. To decrease the radiation loss of the coplanar stripline resonator, a conductor backed coplanar stripline resonator has been proposed which has the unloaded Q of 170.

Junction termination technology for 4H-SiC devices (Junction termination 기법에 따른 4H-SiC 소자의 항복전압 특성 분석)

  • Kim, H.Y.;Bahng, W.;Song, G.H.;Kim, N.K.;Kim, E.D.
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2003.07a
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    • pp.286-289
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    • 2003
  • In the case of high voltage devices, junction termination plays an important role in determining the breakdown voltage of the device. The mesa junction termination has been demonstrated to yield nearly ideal breakdown voltage for 6H-SiC p-n junctions. However, such an approach may not be attractive because of the nonplanar surface, which is difficult to passivate. Moreover, In case of 4H-SiC, ideal breakdown voltage could not be achieved using mesa junction termination. For 4H-SiC planar junction termination technique is more useful one rather than mesa junction termination. In this paper, breakdown characteristics of the 4H-SiC device with planar junction termination, such as FLR(Field Limiting Ring), FP(Field Plate) and JTE(Junction Termination Extension), is presented. In the case of the FLR, breakdown voltage of 1800V is obtained. And breakdown voltage of 1000V and 1150V is also obtained for the case of FP and JTE case, respectively.

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Preparation of High density YIG ferrite by conventional solid-state sintering (고상합성법에 의한 고밀토 YIG 자성체 제조)

  • Kim, Dong-Young;Jun, Dong-Suk;Lee, Hong-Yeol;Lee, Sang-Seok
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2003.07a
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    • pp.533-536
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    • 2003
  • YIG(Yttrium Iron Garnet) is one of the most widely used ferrites for microwave telecommunication. It used as a passive devices such as isolators and circulators. In order to reduce the insertion losses of these passive devices, it is very important to reduce magnetic loss of the ferrites. In general, the magnetic losses of ferrites is closely related to the microstructure of the ceramics. In the sintering of YIG, pores are easily trapped in grains and grain boundaries. These pores cause to increase magnetic losses of the sinterted bodies. In this paper, the effect of the $SiO_2$ addition on the microstructure was discussed. Increasing the $SiO_2$ addition, the grain size was reduced, which means that added acts as a grain-growth inhibitor. During the sintering, $SiO_2$ settled down on the grain boundaries, and drag the grain growth. Therefore, there is enough time for pores to move out. The relative density of YIG sintered at $1350^{\circ}C$ with 1 mol% $SiO_2$ addition was 99.6%. $\Delta$H of these samples was under 50 Oe.

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Thermal Characteristics Analysis of Power Device for Motor Driving Power Converter (전동기 구동용 전력 변환기에 대한 전력소자의 열적 특성 해석)

  • Cho, Moontaek;Lee, Chungsik;Lee, SangBock
    • Journal of the Korean Society of Radiology
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    • v.6 no.6
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    • pp.495-498
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    • 2012
  • In this paper, the basic behavior of the environment and the driving time as a prediction of the lifetime of the power semiconductor devices were recorded. Radiator of a power device driving time and temperature operating environment, including cumulative record by the controller of the power converter, and doing it so you can see the power semiconductor devices for the life of the structure that the size of the change in the temperature of the semiconductor chip and the number of iterations to maintenance warranty period because of a lifetime by forecasting or replacement can be made at the appropriate time that is considered.

Thermal Stability of Self-formed Barrier Stability Using Cu-V Thin Films

  • Han, Dong-Seok;Mun, Dae-Yong;Kim, Ung-Seon;Park, Jong-Wan
    • Proceedings of the Korean Vacuum Society Conference
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    • 2011.02a
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    • pp.188-188
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    • 2011
  • Recently, scaling down of ULSI (Ultra Large Scale Integration) circuit of CMOS (Complementary Meta Oxide Semiconductor) based electronic devices, the electronic devices, become much faster and smaller size that are promising property of semiconductor market. However, very narrow interconnect line width has some disadvantages. Deposition of conformal and thin barrier is not easy. And metallization process needs deposition of diffusion barrier and glue layer for EP/ELP deposition. Thus, there is not enough space for copper filling process. In order to get over these negative effects, simple process of copper metallization is important. In this study, Cu-V alloy layer was deposited using of DC/RF magnetron sputter deposition system. Cu-V alloy film was deposited on the plane SiO2/Si bi-layer substrate with smooth surface. Cu-V film's thickness was about 50 nm. Cu-V alloy film deposited at $150^{\circ}C$. XRD, AFM, Hall measurement system, and AES were used to analyze this work. For the barrier formation, annealing temperature was 300, 400, $500^{\circ}C$ (1 hour). Barrier thermal stability was tested by I-V(leakage current) and XRD analysis after 300, 500, $700^{\circ}C$ (12 hour) annealing. With this research, over $500^{\circ}C$ annealed barrier has large leakage current. However vanadium-based diffusion barrier annealed at $400^{\circ}C$ has good thermal stability. Therefore thermal stability of vanadium-based diffusion barrier is desirable for copper interconnection.

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Flip Chip Bonder for Automactic Parallel Aligning of IR Sensors and Read Out Integrated Circuits (적외선 센서/ROIC 접합을 위한 자동 평행 배열 방식의 플립 칩 본더)

  • Suh, Sang-Hee;Kim, Jin-Sang;An, Se-Young
    • Journal of Sensor Science and Technology
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    • v.10 no.5
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    • pp.337-342
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    • 2001
  • Infrared sensors with one or two dimensional arrays are usually bonded via indium bumps to Si CMOS read out circuits. Therefore, both sensing of infrared beams and processing of signals are performed at the focal plane. This gives us a benefit of reducing noise as well as size of infrared detectors. We have developed a way of boding indium bumps with keeping sensor and ROIC parallel to each other. The flip chip bonder developed has a very simple structure and is easy to operate. So we expect that reliability will be improved very much.

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Enhanced Mutual Authentication Scheme based on Chaotic Map for PCM in NFC Service Environment

  • Park, Sung-Wook;Lee, Im-Yeong
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • v.11 no.2
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    • pp.1180-1200
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    • 2017
  • Currently, automated payment services provide intuitive user interfaces by adapting various wireless communication devices with mobile services. For example, companies like Samsung, Google, and Apple have selected the NFC payment method to service payments of existing credit cards. An electronic payment standard has been released for NFC activation within Korea and will strengthen the safety of payment service communications. However, there are various security risks regarding the NFC-based electronic payment method. In particular, the NFC payment service using the recently released lightweight devices cannot provide the cryptographic strength that is supported by many financial transaction services. This is largely due to its computational complexity and large storage resource requirements. The chaotic map introduced in this study can generate a highly complicated code as it is sensitive to the initial conditions. As the lightweight study using the chaotic map has been actively carried out in recent years, associated authentication techniques of the lightweight environment have been released. If applied with a chaotic map, a high level of cryptographic strength can be achieved that can provide more functions than simple XOR operations or HASH functions. Further, this technique can be used by financial transaction services. This study proposes a mutual authentication technique for NFC-PCM to support an NFC payment service environment based on the chaotic map.

Panoramic Image Generation in Mobile Ad-Hoc Cloud (Mobile Ad-Hoc Cloud 기반 파노라마 이미지 생성)

  • Park, Yong-Suk;Kim, Hyun-Sik;Chung, Jong-Moon
    • Journal of Internet Computing and Services
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    • v.18 no.5
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    • pp.79-85
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    • 2017
  • This paper proposes the use of mobile ad-hoc cloud for reducing the process time of panoramic image generation in mobile smart devices. In order to effectively assign tasks relevant to panoramic image generation to the mobile ad-hoc cloud, a method for image acquisition and sorting and an algorithm for task distribution and offloading decision making are proposed. The proposed methods are applied to Android OS based smart devices, and their effects on panoramic image generation are analyzed.