• The Transactions of The Korean Institute of Electrical Engineers
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• v.68 no.1
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• pp.90-97
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• 2019

The charge redistribution digital-to-analog converter(CR-DAC) is often used for successive approximation register analog-to-digital converter(SAR ADC) that requiring low power consumption and small circuit area. However, CR-DAC is required 2 to the power of N unit capacitors to generate reference voltage for successive approximation of the N-bit SAR ADC, and many unit capacitors occupy large circuit area and consume more power. In order to improve this problem, this paper proposes SAR ADC using series capacitor DAC. The series capacitor DAC is required 2(1+N) unit capacitors to generate reference voltage for successive approximation and charges only two capacitors of the reference generation block. Because of these structural characteristics, the SAR ADC using series capacitor DAC can reduce the power consumption and circuit area. Proposed SAR ADC was designed in CMOS 180nm process, and at 1.8V supply voltage and 500kS/s sampling rate, proposed 6-bit SAR ADC have signal-to-noise and distortion ratio(SNDR) of 36.49dB, effective number of bits(ENOB) of 5.77-bit, power consumption of 294uW.

• Proceedings of the IEEK Conference
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• 2002.07c
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• pp.1401-1403
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• 2002

This paper presents the development of an electronic dash-pot(EDP) system it)r protecting the power electronic circuit. The EDP play role protecting an equipment by disconnecting between voltage source and load system. Also, converting the existed electrical system into an electronic mechanism, it can reduce the power consumption and prevents the system damage due to over current.

• The Journal of the Korea institute of electronic communication sciences
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• v.9 no.9
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• pp.971-976
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• 2014

In this paper, we proposed a low power algorithm using state transition ready method. The proposed algorithm defined a sleep state, a idle state and a run state for the task. A state transition occurring at the time due to the delay time created in order to reduce the power consumption state in the middle of each inserted into the ready state. The ready state considering a power consumption and a delay time in state transition. A scheduling step of performing the steps in excess of the increasing problems have the delay time is long. The power consumption increased for the operation step increase. A state transition from a sleep state with the longest delay time in operating state occurs when the state is switched by the time delay caused by the increase in operating time reduces the overall power consumption reduced. Experiments [6] were compared with the results of the power consumption. The experimental results [6] is reduced power consumption than the efficiency of the algorithm has been demonstrated.

• ETRI Journal
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• v.26 no.6
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• pp.513-519
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• 2004

This paper presents a low power 16-bit adiabatic reduced instruction set computer (RISC) microprocessor with efficient charge recovery logic (ECRL) registers. The processor consists of registers, a control block, a register file, a program counter, and an arithmetic and logical unit (ALU). Adiabatic circuits based on ECRL are designed using a $0.35{\mu}m$ CMOS technology. An adiabatic latch based on ECRL is proposed for signal interfaces for the first time, and an efficient four-phase supply clock generator is designed to provide power for the adiabatic processor. A static CMOS processor with the same architecture is designed to compare the energy consumption of adiabatic and non-adiabatic microprocessors. Simulation results show that the power consumption of the adiabatic microprocessor is about 1/3 compared to that of the static CMOS microprocessor.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.8 no.3
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• pp.857-872
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• 2014

Recent researches reveal that great benefit can be achieved for data gathering in wireless sensor networks (WSNs) by employing mobile data collectors. In order to balance the energy consumption at sensor nodes and prolong the network lifetime, a multi-track large-scale mobile data collection mechanism (MTDCM) is proposed in this paper. MTDCM is composed of two phases: the Energy-balance Phase and the Data Collection Phase. In this mechanism, the energy-balance trajectories, the sleep-wakeup strategy and the data collection algorithm are determined. Theoretical analysis and performance simulations indicate that MTDCM is an energy efficient mechanism. It has prominent features on balancing the energy consumption and prolonging the network lifetime.

• Journal of the Korean Operations Research and Management Science Society
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• v.36 no.1
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• pp.1-11
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• 2011

This article examines the impact of electronic commerce on environmental welfare. In particular, we analyze a game model of price competition between offline and online firms when consumption taxes are imposed on both offline and online transactions that produce environmental pollution. We investigate the properties of optimal taxation between offline and online markets and demonstrate that there is an optimal difference between the two taxes, depending upon not only the transaction cost between offline and online consumption, but also the environmental damage cost. We also investigate the effect of tax-free online transactions on tax revenues, and the financial feasibility of the optimal taxation.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.431-432
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• 2008

We propose a DVS technique for multiprocessor systems considering the energy consumed when translating voltage. We schedule periodic applications on two identical processors throughout a three-stage process; firstly, the computation energy consumption is minimized then the number of voltage translations is minimized. Finally, the result is compared with the schedule with no voltage translation and the one with smaller energy consumption is chosen. Overall, 10.6% energy reduction was achieved.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.11 no.9
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• pp.4320-4333
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• 2017

Energy-efficient virtual resource allocation algorithm has become a hot research topic in cloud computing. However, most of the existing allocation schemes cannot ensure each type of resource be fully utilized. To solve the problem, this paper proposes a virtual machine (VM) allocation algorithm on the basis of multi-dimensional resource, considering the diversity of user's requests. First, we analyze the usage of each dimension resource of physical machines (PMs) and build a D-dimensional resource state model. Second, we introduce an energy-resource state metric (PAR) and then propose an energy-aware multi-dimensional resource allocation algorithm called MRBEA to allocate resources according to the resource state and energy consumption of PMs. Third, we validate the effectiveness of the proposed algorithm by real-world datasets. Experimental results show that MRBEA has a better performance in terms of energy consumption, SLA violations and the number of VM migrations.

• Journal of the Semiconductor & Display Technology
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• v.22 no.1
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• pp.49-53
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• 2023

In this paper, we propose an antirandom pattern-based test method considering power consumption to compensate for the problem that the fault coverage through random test decreases or the test time increases significantly when the DUT circuit structure is complex or large. In the proposed method, a group unit test pattern generation process and rearrangement process are added to improve the problems of long calculation time and high-power consumption, which are disadvantages of the previous antirandom test.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.11 no.10
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• pp.5168-5181
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• 2017

The popularity of augmented reality (AR) applications and games are in high demand. Currently, the best common platform to implement AR services is on a smartphone, as online games, navigators, personal assistants, travel guides are among the most popular applications of smartphones. However, the power consumption of an AR application is extremely high, and therefore, highly adaptable and dynamic low power control schemes must be used. Dynamic voltage and frequency scaling (DVFS) schemes are widely used in smartphones to minimize the energy consumption by controlling the device's operational frequency and voltage. DVFS schemes can sometimes lead to longer response times, which can result in a significant problem for AR applications. In this paper, an AR response time monitor is used to observe the time interval between the AR image input and device's reaction time, in order to enable improved operational frequency and AR application process priority control. Based on the proposed response time monitor and the characteristics of the Linux kernel's completely fair scheduler (CFS) (which is the default scheduler of Android based smartphones), a response time step control (RSC) scheme is proposed which adaptively adjusts the CPU frequency and interactive application's priority. The experimental results show that RSC can reduce the energy consumption up to 10.41% compared to the ondemand governor while reliably satisfying the response time performance limit of interactive applications on a smartphone.