• 전기전자학회논문지
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• 제26권1호
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• pp.43-49
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• 2022

본 논문은 전동기의 저속 영역 운전의 센서리스 기법으로 적합한 고조파 주입 센서리스 제어기법에서 사인파, 삼각파 및 사각파를 주입하여 인가 전압 파형에 따른 센서리스 성능을 비교한다. 본 연구는 영구자석 전동기의 센서리스 기법에 관한 것이다. 1kHz 주파수를 갖는 여러 모양의 파형을 주입하여, 각 파형에 대한 추정된 각도의 오차량을 비교 분석한다. 실험은 HILS(hardware in the loop simulation) 시스템을 이용하였으며, Hardware는 제어보드이며 실시간 시뮬레이터에는 Simulik로 구현된 인버터와 전동기의 모델이 위치한다. 제어 알고리즘은 FPGA 제어보드로 구현하였으며, 이는 10kHz 주파수의 PWM 인터럽트 서비스 루틴, 고조파 주입 및 위치 검출 센서리스 알고리즘 등을 포함한다. HILS 실험을 통해 사인파, 삼각파 및 사각파 고조파 주입시 센서리스 제어 성능을 비교한다.

• ETRI Journal
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• 제29권3호
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• pp.396-398
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• 2007

This letter presents an architecture based on a new double-filter strategy to perform the adaptive in-loop filtering process specified by the H.264/AVC standard. The proposed architecture shows considerable advantages, both in terms of hardware cost and latency, when compared with the approaches found in the most recent literature.

• 대한전자공학회논문지SP
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• 제42권2호
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• pp.27-36
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• 2005

년 논문에서는 MPEG과 JPEG, H.26X 계열 등의 DCT-기반 영상/비디오 컨텐츠에 효과적인 암호화 방법을 제안하였고, 이를 최적화된 하드웨어로 구현하여 고속동작이 가능하도록 하였다. 영상/비디오의 압축, 복원 및 암호화로 인한 많은 연산량을 고려하여 영상의 중요한 정보(DC 및 DPCM계수)만을 암호화 대상 데이터로 선정하여 부분 암호화를 수행하였다. 그 결과 암호화에 소요되는 비용은 원 영상 전체를 암호화하는 비용이 감소하였다. 여기서 Nf는 GOP내의 프레임수이고 PI는 B와 P 프레임에 존재하는 인트라 매크로블록의 수이다. 암호화 알고리즘으로는 다중모드 AES, DES, 그리고 SEED를 선택적으로 사용할 수 있도록 하였다. 제안한 암호화 방법은 C++로 구현한 소프트웨어와 TM-5를 사용하여 약 1,000개의 영상을 대상으로 실험하였다 그 결과 부분 암호화된 영상으로부터 원 영상을 추측할 수 없어 암호화 효과가 충분함을 확인하였으며, 이 때 암호화에 의한 압축률 감소율은 $1.6\%$에 불과하였다. Verilog-HDL로 구현한 하드웨어 암호화 시스템은 하이닉스 $0.25{\mu}m$ CMOS 팬텀-셀 라이브러리를 사용하여 SynopsysTM의 디자인 컴파일러로 합성함으로써 게이트-수준 회로를 구하였다. 타이밍 시뮬레이션은 CadenceTM의 Verilog-XL을 이용해서 수행한 결과 100MHz 이상의 동자 주파수에서 안정적으로 동작함을 확인하였다. 따라서 제안된 암호화 방법 및 구현된 하드웨어는 현재 중요한 문제로 대두되고 있는 종단간(end-to-end) 보안에 대한 좋은 해결책으로 유용하게 사용될 수 있으리라 기대된다.

• ETRI Journal
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• 제27권5호
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• pp.557-562
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• 2005

Low-density parity-check (LDPC) codes have recently emerged due to their excellent performance. However, the parity check (H) matrices of the previous works are not adequate for hardware implementation of encoders or decoders. This paper proposes a hybrid parity check matrix which is efficient in hardware implementation of both decoders and encoders. The hybrid H-matrices are constructed so that both the semi-random technique and the partly parallel structure can be applied to design encoders and decoders. Using the proposed methods, the implementation of encoders can become practical while keeping the hardware complexity of the partly parallel decoder structures. An encoder and a decoder are designed using Verilog-HDL and are synthesized using a $0.35 {\mu}m$ CMOS standard cell library.

• ETRI Journal
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• 제27권5호
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• pp.511-524
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• 2005

In this paper, we propose a novel hardware architecture for an intra-prediction, integer transform, quantization, inverse integer transform, inverse quantization, and mode decision module for the macroblock engine of a new video coding standard, H.264. To reduce the cycle of intra prediction, transform/quantization, and inverse quantization/inverse transform of H.264, a reduction method for cycle overhead in the case of I16MB mode is proposed. This method can process one macroblock for 927 cycles for all cases of macroblock type by processing $4{\times}4$ Hadamard transform and quantization during $16{\times}16$ prediction. This module was designed using Verilog Hardware Description Language (HDL) and operates with a 54 MHz clock using the Hynix $0.35 {\mu}m$ TLM (triple layer metal) library.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 ITC-CSCC -1
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• pp.305-308
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• 2002

This paper proposes a control board that includes PNP function with extensibility and effective allocation of allocation. The object of study is to overcome limited extensity of old systems and it is to reuse the system. The system recognizes automatic subsystem from application of main system with board level that is using hardware and software co-design method. The system has both function of main-board and sub-board. So one system can operate simultaneously such as module of alien system. This system has advantages that are fast execution, according as process functional partition to hardware/ software co-design and board size is reduced as well as offer extensity of development system. We obtained good result with control board for existent Z-80 training kit.

• 한국자동차공학회논문집
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• 제6권2호
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• pp.155-167
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• 1998

The prevalence of microprocessor-based controllers in automotive systems has greatly increased the meed for tools which can be used to validate and test control systems over their full range of operation. The objective of this paper is to develop a real time simulator of an anti-lock braking system and the methodology of using hardware-in-the-loop simulation based on a personal computer. By use of this simulator, the analyses of a commercial electronic control unit as well as the validation of the developed control logics for ABS were performed successfully. The simulator of this research can be traction applied to development of more advanced control system, such as traction control systems, vehicle dynamic control system and so forth.

• International Journal of Control, Automation, and Systems
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• 제1권2호
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• pp.252-256
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• 2003

A biped robot should be designed to be an effective mechanical structure and have smaller hardware system if it is to be a stand-alone structure. This paper shows the design methodology of a biped robot controller using FPGA(Field Programmable Gate Array). A hardware system consists of DSP(Digital Signal Processor) as the main CPU, and FPGA as the motor controller. By using FPGA, more flexible hardware system has been achieved, and more compact and simple controller has been designed.

• 전자통신동향분석
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• 제35권4호
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• pp.34-41
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• 2020

The existing Von Neumann architecture places limits to data processing in AI, a booming technology. To address this issue, research is being conducted on computing architectures and artificial neural networks that simulate neurons and synapses, which are the hardware of the human brain. With high-speed, high-throughput data communication infrastructures, photonic solutions today are a mature industrial reality. In particular, due to the recent outstanding achievements of artificial neural networks, there is considerable interest in improving their speed and energy efficiency by exploiting photonic-based neuromorphic hardware instead of electronic-based hardware. This paper covers recent photonic neuromorphic studies and a classification of existing solutions (categorized into multilayer perceptrons, convolutional neural networks, spiking neural networks, and reservoir computing).

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 1995년도 Proceedings of the Korea Automation Control Conference, 10th (KACC); Seoul, Korea; 23-25 Oct. 1995
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• pp.236-239
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• 1995

It is useful to simulate the human visual function for the purpose of image-processing. In this study, the hardware of the spatial filter with the sensitivity of lateral inhibition is realized by the combination of optical parts with electronic circuits. The diffused film with the characteristics of Gaussian type is prepared as a spatial filter. An object's image is convoluted with the spatial filter. From the difference of the convoluted images, the zero-cross position is detected at video rate. The edge of object is extracted in real-time by the use of this equipment. The resolution of edge changes with the value of the standard deviation of diffused film. In addition, it is possible to extract a directional edge selectively when the spatial filter with directional selectivity is used instead of Gaussian type of spatial filter.