• 한국지능시스템학회:학술대회논문집
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• 한국퍼지및지능시스템학회 1993년도 Fifth International Fuzzy Systems Association World Congress 93
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• pp.917-920
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• 1993

Various forms of hardware alternatives exist for the implementation of fuzzy logic controllers. In this paper, we describe a systematic framework for realizing fuzzy heuristics on programmable-logic-devices. Our approach is suitable for the automated development of fuzzy logic controllers.

• 한국정보처리학회:학술대회논문집
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• 한국정보처리학회 2004년도 추계학술발표논문집(상)
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• pp.199-202
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• 2004

프랙탈 압축 알고리즘에서는 필요에 따라 다양한 분할 방식을 사용하고 있다. 기존에는 분할방식에 따라 다른 isometry 변환계수 값만을 사용하고 있다. 본 논문에서는 이러한 문제를 해결하기 위하여 모든 분할 방식에서 공통적으로 사용할 수 있도록 변환 가능한 isometry 변환계수 방식을 제안하였으며 이를 하드웨어로 구현하였다.

• International Journal of Fuzzy Logic and Intelligent Systems
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• 제4권1호
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• pp.34-39
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• 2004

Huffman coding which has been used in many data compression algorithms is a popular data compression technique used to reduce statistical redundancy of a signal. It has been proposed that the Huffman algorithm can decode efficiently using characteristics of the Huffman tables and patterns of the Huffman codeword. We propose a new Huffman decoding algorithm which used a multi way tree search and present an efficient hardware implementation method. This algorithm has a small logic area and memory space and is optimized for high speed decoding. The proposed Huffman decoding algorithm can be applied for many multimedia systems such as MPEG audio decoder.

• 한국전자통신학회논문지
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• 제3권2호
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• pp.65-70
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• 2008

Digital signal processing (DSP) is the process of taking a signal and performing an algorithm on it to analyze, modify, or better identify that signal.[1] To take advantage of DSP advances, one must have at least a basic understanding of DSP theory along with an understanding of the hardware architecture designed to support these new advances. There are several programming techniques that maximize the efficiency of the DSP hardware, as well as a few fundamental concepts used to implement DSP software. This article introduced some of these underlying functions that are the building blocks of complex signal processing functions, and It will touch on the fundamental concepts of DSP theory and algorithms and also provide an overview of the implementation and optimization of DSP software, and discuss the development of DSP.

• 대한의용생체공학회:학술대회논문집
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• 대한의용생체공학회 1994년도 추계학술대회
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• pp.92-95
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• 1994

As computer systems to make medical practice easy are widely used, a special hardware system processing medical data fast becomes more important. To meet the urgent demand for high speed image processing, especially image compression and decompression, we designed and implemented the medical image CODEC (COder/BECoder) based on MISD(Multiple Instruction Single Data stream) architecture to adopt parallelism in it. Considering not being a standart scheme of medical mage compression/decompress ion, the CODEC is designed programable and general. In this paper, we use JPEG (Joint Photographic Experts Group) algorithm to process images fast and evalutate it.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2001년도 기술교육위원회 창립총회 및 학술대회 의료기기전시회
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• pp.34-37
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• 2001

This research suggested the new algorithm controlled by micro processor which is already stored by various PWM form of output voltage by using fundamental data of the carrier and signal. The determined PWM pattern is not concerned with the signal wave form and the new algorithm can obtain the desired pulse width by synchronous of carrier. The PWM wave can be controlled with real time by using extra hardware and digital software and to speed up program processing, the control signals to switch the power semi-conductor of three phase PWM inverter, simultaneously use the output signal by microprocessor and extra hardware, and control signal by software. In the end, this method was proved by applying to Three phase voltage source inverter.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1992년도 하계학술대회 논문집 A
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• pp.245-247
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• 1992

We utilize as a processor TMS320C25 (Texas Instrument) in making a driver for a 4 pole PM synchronous servo motor. TMS320C25 has a 32bit ALU and a 16 bit hardware multiplier, and the maximum instruction execution rate is 10MIPS at 40MHz. We adopted a space vector modulation PWM method. An interesting point of this work is that PWM wave is generated by utilizing timer interrupts. Hence, in the rest of time the processor can take care of the other routine such as Park's coordinate transformation and the computation required in the feedback loops. Thus, it mates the hardware circuit very simple. Due to the decrease in the number of components, the motor drive system becomes more fault-tolerant and cost-optimized. Also, more flexibility is gained in changing the control parameters.

• 한국정밀공학회지
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• 제29권11호
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• pp.1174-1177
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• 2012

In voltage measurement by using voltage divider with series resistors, error is generated caused by the variation of resistance. In order to reduce these errors, the hardware cost tends to increase in the previous works. In the proposed method, three resistors are used for the voltage divider of which the organization is adjusted by using switches. Three voltages are measured and the ratio of resistance is calculated based on the measured voltages. Since the resistance ratio is calculated by measuring voltages and additional hardware cost is minimal, the voltage can be measured with high accuracy and low cost. Experimental results show that the mean absolute error is 12.1 mV when the input voltage ranges from 5 V to 50 V.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2001년도 하계학술대회 논문집 A
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• pp.237-239
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• 2001

This paper describes the digital relay simulator system using digital signal processor. The simulator system has two parts, one is software and the other is hardware part. The simulation software has variety calculation engines ; EMTP simulation data file conversion, user define simulation data generation, sequence data generation, data analysis engines. etc, these are designed upon GUI. And simulator software provides easy control interface for users, the simulator software performs on every MS Windows OS. The simulator hardware design uses 32bit floating point DSP(TMS320C32) architecture to achieve flexibility and high speed operation.

• Transactions on Electrical and Electronic Materials
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• 제13권6호
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• pp.278-282
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• 2012

Photovoltaic systems have emerged to be one of the cleanest energy systems. Therefore, many large scale solar parks and PV farms have been built to prepare for the post fossil fuel ages. However, due to their large scale, to efficiently manage and operate PV systems, they need to be visually monitored within the range of infrared ray through the Internet. To satisfy this need, the efficient implementation of a high performance video compression standard is required. This paper therefore presents an implementation of H.264 motion estimation, which is one of the most data-intensive and complicated functions in H.264. To achieve this, this work implements vector instructions in hardware and incorporates them in a generic RISC processor architecture, thus increasing the processing speed while minimizing hardware and software design efforts. Extensive simulation results show that this proposed implementation can process motion estimations up to 13 times faster.