• JSTS:Journal of Semiconductor Technology and Science
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• 제16권5호
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• pp.564-581
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• 2016

We present an efficient hardware prime generator that generates a prime p by combining trial division and Fermat test in parallel. Since the execution time of this parallel combination is greatly influenced by the number k of the smallest odd primes used in the trial division, it is important to determine the optimal k to create the fastest parallel combination. We present probabilistic analysis to determine the optimal k and to estimate the expected running time for the parallel combination. Our analysis is conducted in two stages. First, we roughly narrow the range of optimal k by using the expected values for the random variables used in the analysis. Second, we precisely determine the optimal k by using the exact probability distribution of the random variables. Our experiments show that the optimal k and the expected running time determined by our analysis are precise and accurate. Furthermore, we generalize our analysis and propose a guideline for a designer of a hardware prime generator to determine the optimal k by simply calculating the ratio of M to D, where M and D are the measured running times of a modular multiplication and an integer division, respectively.

• 대한전자공학회논문지SD
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• 제43권11호
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• pp.19-25
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• 2006

RTOS(Real Time Operating System)의 빠른 수행 능력은 임베디드 시스템의 성능을 결정하는 중요한 요소이다. 멀티미디어 및 통신 환경이 발달하면서 더 높은 처리 성능의 시스템을 요구하고 있다. 그러나 마이크로프로세서를 기반으로 하는 소프트웨어로 이루어진 RTOS의 처리 능력을 획기적으로 개선하는 데는 어려운 점이 많다. 따라서 본 논문에서는 RTOS의 성능을 개선하기 위하여 소프트웨어로 이루어진 일부 기능을 하드웨어로 구현하기 위한 Silicon RTOS의 구성에 대하여 연구하였으며 실제로 uC/OS-II의 해당 부분을 하드웨어로 구현하였으며 성능을 비교 분석하였다.

• Journal of Power Electronics
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• 제11권4호
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• pp.471-478
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• 2011

This paper addresses the establishment of a kVA-range plug-in hybrid electrical vehicle (PHEV) integration test platform and associated issues. Advancements in battery and power electronic technology, hybrid vehicles are becoming increasingly dependent on the electrical energy provided by the batteries. Minimal or no support by the internal combustion engine may result in the vehicle being occasionally unable to recharge the batteries during highly dynamic driving that occurs in urban areas. The inability to sustain its own energy source creates a situation where the vehicle must connect to the electrical grid in order to recharge its batteries. The effects of a large penetration of electric vehicles connected into the grid are still relatively unknown. This paper presents a novel methodology that will be utilized to study the effects of PHEV charging at the sub-transmission level. The proposed test platform utilizes the power hardware-in-the-loop (PHIL) concept in conjunction with high-fidelity PHEV energy system simulation models. The battery, in particular, is simulated utilizing a real-time digital simulator ($RTDS^{TM}$) which generates appropriate control commands to a power electronics-based voltage amplifier that interfaces via a LC-LC-type filter to a power grid. In addition, the PHEV impact is evaluated via another power electronic converter controlled through $dSPACE^{TM}$, a rapid control systems prototyping software.

• 전기학회논문지
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• 제65권12호
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• pp.2030-2036
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• 2016

This paper presents a hardware development procedure of the ASB(Active Seat Belt) control system to comply with ISO 26262. The ASIL(Automotive Safety Integrity Level) of an ASB system is determined through the HARA(Hazard Analysis and Risk Assessment) and the safety mechanism is applied to meet the reqired ASIL. The hardware architecture of the controller consists of a microcontroller, H-bridge circuits, passive components, and current sensors which are used for the input comparison. The required ASIL for the control systems is shown to be satisfied with the safety mechanism by calculation of the SPFM(Single Point Fault Metric) and the LFM(Latent Fault Metric) for the design circuits.

• Journal of Communications and Networks
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• 제13권1호
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• pp.70-76
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• 2011

This paper presents the unified user equipment (UE) baseband modulation and demodulation (modem) hardware platform architecture to support multiple radio access technologies. In particular, this platform selectively supports two systems; one is HEDGE system, which is the combination of third generation partnership project (3GPP) Release 7 high speed packet access evolution (HSPA+) and global system for mobile communication (GSM)/general packet radio service (GPRS)/enhanced data rates for GSM evolution (EDGE), while the other is LEDGE system, which is the combination of 3GPP Release 8 long term evolution (LTE) and GSM/GPRS/EDGE. This is done by applying the flexible pin multiplexing scheme to a hardwired pin mapping process. On the other hand, to provide stable connection, high portability, and high debugging ability, the stacking structure is employed. Here, a layered board architecture grouped by functional classifications is applied instead of the conventional one flatten board. Based on this proposed configuration, we provide a framework for the verification step in wireless cellular communications. Also, modem function/scenario test and inter-operability test with various base station equipments are verified by system requirements and scenarios.

• Journal of information and communication convergence engineering
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• 제3권4호
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• pp.205-208
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• 2005

This paper is about the hardware implementation of the Hash algorithm, HAS-160, which is widely used for Internet security and authentication. VHDL modeling was used for its realization and the operation speed has been increased by the optimized scheduling of the operations required for step operations.

• Journal of information and communication convergence engineering
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• 제3권4호
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• pp.201-204
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• 2005

Twofish is a 128-bit block cipher that accepts a variable-length key up to 256 bits. The cipher is a 16­round Feistel network with a bijective F function made up of four key-dependent 8-by-8-bit S-boxes, a fixed 4­by-4 maximum distance separable matrix over Galois Field$(GF (2^8)$, a pseudo-Hadamard transform, bitwise rotations, and a carefully designed key schedule. In this paper, the Twofish is modeled in VHDL and simulated. Hardware implementation gives much better performance than software-based approaches.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2005년도 학술대회 논문집 전문대학교육위원
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• pp.122-127
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• 2005

This paper proposes a prototype IED hardware design and it's real-time experimental results. To evaluate performance of the IED, the study is well constructed power system model including power transformer utilizing the EMTP software and the testing is made through simulation of various cases. The relaying that is well constructed using DSP chip and RISC CPU etc. has been developed and the prototype IED has been verified through on-line testing by LabVIEW simulator. The results show that an advanced relaying based prototype IED never mis-operated.

• 한국통신학회:학술대회논문집
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• 한국통신학회 2006년도 하계종합학술발표회 논문 초록집
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• pp.403-403
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• 2006

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2006년도 하계종합학술대회
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• pp.451-452
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• 2006

In this paper, we present a 3D reconstruction method using multi-camera. This method is very compact algorithm so that can be implemented easily on small hardware architecture. By using multi-camera, it gives exacter result than existing method and we propose accurate index for each matching nodes to use multi-camera.