• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.14 no.4
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• pp.300-306
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• 2021

Due to the development of IT technology, hardware technologies applied to IoT equipment have recently been developed, so smart systems using low-cost, high-performance RF and computing devices are being developed. However, in the infrastructure environment where a large amount of IoT devices are installed, big data collection causes a load on the collection server due to a bottleneck between the transmitted data. As a result, data transmitted to the data collection server causes packet loss and reduced data throughput. Therefore, there is a need for an efficient big data collection technique in an infrastructure environment where a large amount of IoT devices are installed. Therefore, in this paper, we propose an efficient big data collection technique in an infrastructure environment where a vast amount of IoT devices are installed. As a result of the performance evaluation, the packet loss and data throughput of the proposed technique are completed without loss of the transmitted file. In the future, the system needs to be implemented based on this design.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.21 no.2
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• pp.137-142
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• 2021

A Photovoltaic power streetlight is a system that uses solar energy to charge a secondary battery and then uses it for night lighting through a lamp, and can be configured as a standalone or grid-connected type by installing an LED streetlight at the load end. The energy generated through the solar cell module can be charged to the secondary battery through the charge/discharge control device, and then the LED street light can be turned on and off by comparing the power generation voltage and the charging voltage according to the monitoring of solar radiation, or by setting a specific time after sunset or sunrise. Based on these contents, this paper designed and manufactured a simulated solar power streetlight for education using new and renewable energy utilization and storage functions. Using these educational equipment, students can 1) understand the flow of energy change using renewable energy including sunlight as electric energy, 2) understand new and renewable energy, and cultivate basic design and manufacturing application power of related products, 3) The use of new and renewable energy through power conversion and strengthening of practical training and analysis through hardware production can be instilled.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.18 no.6A
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• pp.39-49
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• 2008

AEA and ARIA are next generation standard block cipher of US and Korea, respectively, and these algorithms are used in various fields including smart cards, electronic passport, and etc. This paper addresses the first efficient unified hardware architecture of AES and ARIA, and shows the implementation results with 0.25um CMOS library. We designed shared S-boxes based on composite filed arithmetic for both algorithms, and also extracted common terms of the permutation matrices of both algorithms. With the $0.25-{\mu}m$ CMOS technology, our processor occupies 19,056 gate counts which is 32% decreased size from discrete implementations, and it uses 11 clock cycles and 16 cycles for AES and ARIA encryption, which shows 720 and 1,047 Mbps, respectively.

• The Journal of Korean Institute of Information Technology
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• v.17 no.5
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• pp.47-55
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• 2019

As the damage caused by GPS jamming has been increased, researches for detecting and preventing GPS jamming is being actively studied. This paper deals with a GPS jamming detection method using multiple GPS receiving channels and three-types machine learning techniques. Proposed multiple GPS channels consist of commercial GPS receiver with no anti-jamming function, receiver with just anti-noise jamming function and receiver with anti-noise and anti-spoofing jamming function. This system enables user to identify the characteristics of the jamming signals by comparing the coordinates received at each receiver. In this paper, The five types of jamming signals with different signal characteristics were entered to the system and three kinds of machine learning methods(AB: Adaptive Boosting, SVM: Support Vector Machine, DT: Decision Tree) were applied to perform jamming detection test. The results showed that the DT technique has the best performance with a detection rate of 96.9% when the single machine learning technique was applied. And it is confirmed that DT technique is more effective for GPS jamming detection than the binary classifier techniques because it has low ambiguity and simple hardware. It was also confirmed that SVM could be used only if additional solutions to ambiguity problem are applied.

• Journal of Korean Society of Industrial and Systems Engineering
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• v.44 no.1
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• pp.60-70
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• 2021

Recently, with the development of technologies for the fourth industrial revolution, convergence and complex technology are being applied to aircraft, electronic home appliances and mobile devices, and the number of parts used is increasing. Increasing the number of parts and the application of convergence technologies such as HW (hardware) and SW (software) are increasing the No Defect Found (NDF) phenomenon in which the defect is not reproduced or the cause of the defect cannot be identified in the subsequent investigation systems after the discovery of the defect in the product. The NDF phenomenon is a major problem when dealing with complex technical systems, and its consequences may be manifested in decreased safety and dependability and increased life cycle costs. Until now, NDF-related prior studies have been mainly focused on the NDF cost estimation, the cause and impact analysis of NDF in qualitative terms. And there have been no specific methodologies or examples of a working-level perspective to reduce NDF. The purpose of this study is to present a practical methodology for reducing NDF phenomena through data mining methods using quantitative data accumulated in the enterprise. In this study, we performed a cluster analysis using market defects and design-related variables of mobile devices. And then, by analyzing the characteristics of groups with high NDF ratios, we presented improvement directions in terms of design and after service policies. This is significant in solving NDF problems from a practical perspective in the company.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.24 no.2
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• pp.179-185
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• 2020

Recently, in order to improve the performance of the Earthquake Early Warning System (EEWS) and to supplement the effects of earthquake disaster prevention in epicenters or near epicenters, development of on-site EEWS has been attempted. Unlike the national EEWS, which is used for earthquake disaster prevention by using seismic observation networks for earthquake research and observation, on-site EEWS aims at earthquake disaster prevention and therefore requires efficient design and evaluation in terms of performance and cost. At present, Korea lacks the necessary core technologies and operational know-how, including the use of existing EEWS design criteria and evaluation methods for the development of On-Site EEWS as well as EEWS. This study proposes hardware and software design directions and performance evaluation items and methods for seismic data collection, data processing, and analysis for localization of On-Site EEWS based on the seismic accelerometer requirements of the Seismic and Volcanic Disaster Response Act.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.23 no.10
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• pp.1298-1304
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• 2019

Since the 9·11 terror attack in 2001, the Maritime Logistics Security System has been strengthened and required X-ray image for every imported cargos from manufacturing countries to United States. For scanning cargos, the container inspection systems use high energy X-rays for examination of contents of a container to check the nuclear, explosive, dangerous and illegal materials. Nowadays, the X-ray cargo scanners are established and used by global technologies for inspection of suspected cargos in the customs agency but these technologies have not been localized and developed sufficiently. In this paper, we propose the X-ray array detector system which is a core component of the container scanning system. For implementation of X-ray array detector, the analog and digital signal processing units are fabricated with integrated hardware, FPGA logics and GUI software for real-time X-ray images. The implemented system is superior in terms of resolution and power consumption compared to the existing products currently used in ports.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.25 no.8
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• pp.1095-1102
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• 2021

A scalable ECC architecture with high scalability and flexibility between performance and hardware complexity is proposed. For architectural scalability, a modular arithmetic unit based on a one-dimensional array of processing element (PE) that performs finite field operations on 32-bit words in parallel was implemented, and the number of PEs used can be determined in the range of 1 to 8 for circuit synthesis. A scalable algorithms for word-based Montgomery multiplication and Montgomery inversion were adopted. As a result of implementing scalable ECC processor (sECCP) using 180-nm CMOS technology, it was implemented with 100 kGEs and 8.8 kbits of RAM when N_PE=1, and with 203 kGEs and 12.8 kbits of RAM when N_PE=8. The performance of sECCP with N_PE=1 and N_PE=8 was analyzed to be 110 PSMs/sec and 610 PSMs/sec, respectively, on P256R elliptic curve when operating at 100 MHz clock.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.26 no.6
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• pp.850-858
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• 2022

To deploy Gate Recurrent Units (GRU) on resource-constrained embedded devices, this paper presents a reconfigurable FPGA-based GRU accelerator that enables structured compression. Firstly, a dense GRU model is significantly reduced in size by hybrid quantization and structured top-k pruning. Secondly, the energy consumption on external memory access is greatly reduced by the proposed reuse computing pattern. Finally, the accelerator can handle a structured sparse model that benefits from the algorithm-hardware co-design workflows. Moreover, inference tasks can be flexibly performed using all functional dimensions, sequence length, and number of layers. Implemented on the Intel DE1-SoC FPGA, the proposed accelerator achieves 45.01 GOPs in a structured sparse GRU network without batching. Compared to the implementation of CPU and GPU, low-cost FPGA accelerator achieves 57 and 30x improvements in latency, 300 and 23.44x improvements in energy efficiency, respectively. Thus, the proposed accelerator is utilized as an early study of real-time embedded applications, demonstrating the potential for further development in the future.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.15 no.2
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• pp.124-133
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• 2022

With the development of hardware technology and the advancement of numerical model methods, more precise weather forecasts can be carried out. In this paper, we propose a Unicon Optimization scheme combining Loop Vectorization, Dependency Vectorization, and Code Modernization to optimize and increase Maintainability the Unicon source contained in SCAM, a simplified version of CESM, and present an overall SCAM structure. This paper tested the unicorn optimization scheme in the SCAM structure, and compared to the existing source code, the loop vectorization resulted in a performance improvement of 3.086% and the dependency vectorization of 0.4572%. And in the case of Unicorn Optimization, which applied all of these, the performance improvement was 3.457% compared to the existing source code. This proves that the Unicorn Optimization technique proposed in this paper provides excellent performance.