• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.887-888
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• 2006

In this paper, we devised mac-yule detection system which provide resting state mac-yule. The devised system composed of signal transformation part, signal processing part, and PC based display part. Hardware part consisit of PPG, ECG, EEG, EMG, and RSP. Also, software system consist of bio-signal processing software which detecting mac-yule. EEG-$\alpha$, $\beta$ wave analysis algorithm that use wavelet transformation, RSP detecting algorithm which used zero-crossing method.

• Journal of Power Electronics
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• v.11 no.2
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• pp.202-210
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• 2011

Polymer electrolyte membrane (PEM) fuel cell is one of the popular renewable energy sources and widely used in commercial medium power areas from portable electronic devices to electric vehicles. In addition, the increased integration of the PEM fuel cell with power electronics, dynamic loads, and control systems requires accurate electrical models and simulation methods to emulate their electrical behaviors. Advancement in parallel computation techniques, various real-time simulation tools, and smart power hardware have allowed the prototyping of novel apparatus to be investigated in a virtual system under a wide range of realistic conditions repeatedly, safely, and economically. This paper builds up advancements of optimized model constructions for a fuel cell stack system on a real-time simulator in the view points of improving dynamic model accuracy and boosting computation speed. In addition, several considerations for a power hardware-in-the-loop (PHIL) simulation are provided to electrically emulate the PEM fuel cell stack system with power facilities. The effectiveness of the proposed PHIL simulation method developed on Opal RT's RT-Lab Matlab/Simulink based real-time engineering simulator and a programmable power supply is verified using experimental results of the proposed PHIL simulation system with a Ballard Nexa fuel cell stack.

• Journal of Biosystems Engineering
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• v.37 no.3
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• pp.148-154
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• 2012

Purpose: In order to improve road-friendliness of heavy vehicles, a fuzzy hybrid control strategy consisting of a hybrid control strategy and a fuzzy logic control module is proposed. The performance of the proposed strategy should be effectively evaluated using a hardware-in-the-loop (HIL) simulation model of a semi-active suspension system based on the fuzzy hybrid control strategy prior to real vehicle implementations. Methods: A hardware-in-the-loop (HIL) simulation system was synthesized by utilizing a self-developed electronic control unit (ECU), a PCI-1711 multi-functional data acquisition board as well as the previously developed quarter-car simulation model. Road-friendliness of a semi-active suspension system controlled by the proposed control strategy was simulated via the HIL system using Dynamic Load Coefficient (DLC) and Dynamic Load Stress Factor (DLSF) criteria. Results: Compared to a passive suspension, a semi-active suspension system based on the fuzzy hybrid control strategy reduced the DLC and DLSF values. Conclusions: The proposed control strategy of semi-active suspension systems can be employed to improve road-friendliness of road vehicles.

• Journal of Broadcast Engineering
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• v.17 no.2
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• pp.374-387
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• 2012

In this paper, we implement a new hardware for finding the significant coefficients of a digital hologram and ciphering them using discrete wavelet packet transform (DWPT). Discrete wavelet transform (DWT) and packetization of subbands is used, and the adopted ciphering technique can encrypt the subbands with various robustness based on the level of the wavelet transform and the threshold of subband energy. The hologram encryption consists of two parts; the first is to process DWPT, and the second is to encrypt the coefficients. We propose a lifting based hardware architecture for fast DWPT and block ciphering system with multi-mode for the various types of encryption. The unit cell which calculates the repeated arithmetic with the same structure is proposed and then it is expanded to the lifting kernel hardware. The block ciphering system is configured with three block cipher, AES, SEED and 3DES and encrypt and decrypt data with minimal latency time(minimum 128 clocks, maximum 256 clock) in real time. The information of a digital hologram can be hided by encrypting 0.032% data of all. The implemented hardware used about 200K gates in $0.25{\mu}m$ CMOS library and was stably operated with 165MHz clock frequency in timing simulation.

• Journal of IKEEE
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• v.24 no.3
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• pp.901-908
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• 2020

This paper describes a method for scalable hardware implementation of modular inversion. The proposed scalable architecture has a one-dimensional array of processing elements (PEs) that perform arithmetic operations in 32-bit word, and its performance and hardware size can be adjusted depending on the number of PEs used. The hardware operation of the scalable processor for modular inversion was verified by implementing it on Spartan-6 FPGA device. As a result of logic synthesis with a 180-nm CMOS standard cells, the operating frequency was estimated to be in the range of 167 to 131 MHz and the gate counts were in the range of 60,000 to 91,000 gate equivalents when the number of PEs was in the range of 1 to 10. When calculating 256-bit modular inverse, the average performance was 18.7 to 118.2 Mbps, depending on the number of PEs in the range of 1 to 10. Since our scalable architecture for computing modular inversion in GF(p) has the trade-off relationship between performance and hardware complexity depending on the number of PEs used, it can be used to efficiently implement modular inversion processor optimized for performance and hardware complexity required by applications.

• 제어로봇시스템학회:학술대회논문집
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• 1987.10a
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• pp.851-856
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• 1987

A direct computation algorithm of two dimensional fast Fourier transform (2D-FFT) is considered here for implementation in mesh connected multiprocessor array of both a 2D-toroidal and a rectangular type. Results are derived for a hardware algorithm including data allocation and interprocessor communications. A performance comparison is carried out between the proposed direct 2D-FFT computation and the conventional one to show that a new algorithm gives higher speedup under a reasonable assumption on the speeds of operations.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.603-604
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• 2008

This paper implemented The LED illuminance control IP based on 8bit RISC Processor. 8bit RISC Processor designed hardware interrupts, an interface for serial communications, a timer system with compare-capture-reload resources and a watchdog timer. LED Array consists of Red, Green, Blue, White and Warm White. The illuminance control IP is used to LED Board control with 8bit data.

• Proceedings of the KIPE Conference
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• 1998.10a
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• pp.642-647
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• 1998

A new small-signal model for the controlled on-time boost power factor correction (PFC) circuit is presented. The proposed small-signal model is valid up to high frequencies over lKHz. The model can be used in designing the voltage feedback compensation of PFC circuits, the control bandwidth of which is maximized with auxiliary means of removing the low-frequency ripple from the output. The accuracy of the model is confirmed by a 200W experimental hardware

• Proceedings of the KIPE Conference
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• 2003.07b
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• pp.769-772
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• 2003

In this paper are described design of hardware and GUI(Graphical User Interface) for a PC based Weighting System. Conventional Weighting System is adapted microprocessor system for measuring and controlling. This system should have big memory for the management of measured data and is difficult to operate. For such reason a new Weighting System based on PC is proposed. In this contribution is handled these problems.

• Proceedings of the KIEE Conference
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• 1988.07a
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• pp.691-694
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• 1988

This paper proposes the model of Image Display on the Xenix System V and describes the method of writing device driver which can drive the graphics hardware and image scanner. The interface between user program and device driver in Kernel is also presented.