• Journal of IKEEE
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• v.26 no.1
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• pp.43-49
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• 2022

This paper compares the sensorless control performance according to the applied voltage waveform by injecting sinusoidal, triangular, and square waveform in the harmonic injection sensorless control method. By injecting various voltage shape waveform with a frequency of 1kHz, the error amount of the estimated angle for each waveform is compared and analyzed. For the experiment, the HILS(hardware in the loop simulation) system was used. The hardware is the control board, and the inverter and motor models implemented in Simulik are located in the real-time simulator. The control algorithm is implemented by the FPGA control board, which includes a PWM interrupt service routine with a frequency of 10 kHz, harmonic injection and position detection sensorless algorithm.

• ETRI Journal
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• v.29 no.3
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• pp.396-398
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• 2007

This letter presents an architecture based on a new double-filter strategy to perform the adaptive in-loop filtering process specified by the H.264/AVC standard. The proposed architecture shows considerable advantages, both in terms of hardware cost and latency, when compared with the approaches found in the most recent literature.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.42 no.2 s.302
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• pp.27-36
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• 2005

This thesis proposed an effective encryption method for the DCT-based image/video contents and made it possible to operate in a high speed by implementing it as an optimized hardware. By considering the increase in the amount of the calculation in the image/video compression, reconstruction and encryption, an partial encryption was performed, in which only the important information (DC and DPCM coefficients) were selected as the data to be encrypted. As the result, the encryption cost decreased when all the original image was encrypted. As the encryption algorithm one of the multi-mode AES, DES, or SEED can be used. The proposed encryption method was implemented in software to be experimented with TM-5 for about 1,000 test images. From the result, it was verified that to induce the original image from the encrypted one is not possible. At that situation, the decrease in compression ratio was only $1.6\%$. The hardware encryption system implemented in Verilog-HDL was synthesized to find the gate-level circuit in the SynopsysTM design compiler with the Hynix $0.25{\mu}m$ CMOS Phantom-cell library. Timing simulation was performed by Verilog-XL from CadenceTM, which resulted in the stable operation in the frequency above 100MHz. Accordingly, the proposed encryption method and the implemented hardware are expected to be effectively used as a good solution for the end-to-end security which is considered as one of the important problems.

• ETRI Journal
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• v.27 no.5
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• pp.557-562
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• 2005

Low-density parity-check (LDPC) codes have recently emerged due to their excellent performance. However, the parity check (H) matrices of the previous works are not adequate for hardware implementation of encoders or decoders. This paper proposes a hybrid parity check matrix which is efficient in hardware implementation of both decoders and encoders. The hybrid H-matrices are constructed so that both the semi-random technique and the partly parallel structure can be applied to design encoders and decoders. Using the proposed methods, the implementation of encoders can become practical while keeping the hardware complexity of the partly parallel decoder structures. An encoder and a decoder are designed using Verilog-HDL and are synthesized using a $0.35 {\mu}m$ CMOS standard cell library.

• ETRI Journal
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• v.27 no.5
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• pp.511-524
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• 2005

In this paper, we propose a novel hardware architecture for an intra-prediction, integer transform, quantization, inverse integer transform, inverse quantization, and mode decision module for the macroblock engine of a new video coding standard, H.264. To reduce the cycle of intra prediction, transform/quantization, and inverse quantization/inverse transform of H.264, a reduction method for cycle overhead in the case of I16MB mode is proposed. This method can process one macroblock for 927 cycles for all cases of macroblock type by processing $4{\times}4$ Hadamard transform and quantization during $16{\times}16$ prediction. This module was designed using Verilog Hardware Description Language (HDL) and operates with a 54 MHz clock using the Hynix $0.35 {\mu}m$ TLM (triple layer metal) library.

• Proceedings of the IEEK Conference
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• 2002.07a
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• pp.305-308
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• 2002

This paper proposes a control board that includes PNP function with extensibility and effective allocation of allocation. The object of study is to overcome limited extensity of old systems and it is to reuse the system. The system recognizes automatic subsystem from application of main system with board level that is using hardware and software co-design method. The system has both function of main-board and sub-board. So one system can operate simultaneously such as module of alien system. This system has advantages that are fast execution, according as process functional partition to hardware/ software co-design and board size is reduced as well as offer extensity of development system. We obtained good result with control board for existent Z-80 training kit.

• Transactions of the Korean Society of Automotive Engineers
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• v.6 no.2
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• pp.155-167
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• 1998

The prevalence of microprocessor-based controllers in automotive systems has greatly increased the meed for tools which can be used to validate and test control systems over their full range of operation. The objective of this paper is to develop a real time simulator of an anti-lock braking system and the methodology of using hardware-in-the-loop simulation based on a personal computer. By use of this simulator, the analyses of a commercial electronic control unit as well as the validation of the developed control logics for ABS were performed successfully. The simulator of this research can be traction applied to development of more advanced control system, such as traction control systems, vehicle dynamic control system and so forth.

• International Journal of Control, Automation, and Systems
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• v.1 no.2
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• pp.252-256
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• 2003

A biped robot should be designed to be an effective mechanical structure and have smaller hardware system if it is to be a stand-alone structure. This paper shows the design methodology of a biped robot controller using FPGA(Field Programmable Gate Array). A hardware system consists of DSP(Digital Signal Processor) as the main CPU, and FPGA as the motor controller. By using FPGA, more flexible hardware system has been achieved, and more compact and simple controller has been designed.

• Electronics and Telecommunications Trends
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• v.35 no.4
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• pp.34-41
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• 2020

The existing Von Neumann architecture places limits to data processing in AI, a booming technology. To address this issue, research is being conducted on computing architectures and artificial neural networks that simulate neurons and synapses, which are the hardware of the human brain. With high-speed, high-throughput data communication infrastructures, photonic solutions today are a mature industrial reality. In particular, due to the recent outstanding achievements of artificial neural networks, there is considerable interest in improving their speed and energy efficiency by exploiting photonic-based neuromorphic hardware instead of electronic-based hardware. This paper covers recent photonic neuromorphic studies and a classification of existing solutions (categorized into multilayer perceptrons, convolutional neural networks, spiking neural networks, and reservoir computing).

• 제어로봇시스템학회:학술대회논문집
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• 1995.10a
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• pp.236-239
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• 1995

It is useful to simulate the human visual function for the purpose of image-processing. In this study, the hardware of the spatial filter with the sensitivity of lateral inhibition is realized by the combination of optical parts with electronic circuits. The diffused film with the characteristics of Gaussian type is prepared as a spatial filter. An object's image is convoluted with the spatial filter. From the difference of the convoluted images, the zero-cross position is detected at video rate. The edge of object is extracted in real-time by the use of this equipment. The resolution of edge changes with the value of the standard deviation of diffused film. In addition, it is possible to extract a directional edge selectively when the spatial filter with directional selectivity is used instead of Gaussian type of spatial filter.