• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.15 no.11
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• pp.958-962
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• 2002

This paper reports on the fabrication of free-standing microstructures by DRIE (deep reactive ion etching). SOI (Si-on-insulator) structures with buried cavities are fabricated by SDB (Si-wafer direct bonding) technology and electrochemical etch-stop. The cavity was formed the upper handling wafer by Si anisotropic etch technique. SDB process was performed to seal the formed cavity under vacuum condition at -760 mmHg. In the SDB process, captured air and moisture inside of the cavities were removed by making channels towards outside. After annealing (100$0^{\circ}C$, 60 min.), the SDB SOI structure with a accurate thickness and a good roughness was thinned by electrochemical etch-stop in TMAH solution. Finally, it was fabricated free-standing microstructures by DRIE. This result indicates that the fabrication technology of free-standing microstructures by combination SDB, electrochemical etch-stop and DRIE provides a powerful and versatile alternative process for high-performance bulk micromachining in MEMS fields.

• Applied Chemistry for Engineering
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• v.24 no.5
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• pp.562-565
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• 2013

The high purity Al foil, which has an enlarged surface area by electrochemical etching process, has been used as an anode for an aluminum electrolytic capacitor. Etch pits are randomly distributed on the surface because of the existence of surface irregularities such as impurity and random nucleation of pits. Even though a large surface area was formed on the tunnel-etched Al, its applications to various fields were limited due to non-uniform tunnel morphologies. In this work, the selective electrochemical etching of aluminum was carried out by using a patterned mask fabricated by photolithographic method. The formation of etch pits with uniform distribution has been demonstrated by the optimization of experimental conditions such as current density and etching solution temperature.

• Proceedings of the KIEE Conference
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• 1989.07a
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• pp.295-298
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• 1989

Using the anisotropic etching characteristics or $N_2H_4-H_2O$ solution, Si diaphragm was fabricated for the integrated sensor. The optimal composition and temperature of the solution in Si etching process was established to be 50mol% $N_2H_4$ in water at $105{\pm}2^{\circ}C$ for both higher etch rate(=$2.6{\mu}m/min$) and better surface quality of etched {100} planes. Under the optimal etching condition, the electrochemical etch stop technique was employed to form Si diaphragm for pressure sensor and diaphragm thickness was exactly controlled to $20{\pm}2{\mu}m$.

• Journal of the Korean Electrochemical Society
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• v.11 no.2
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• pp.100-104
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• 2008

Titanium sheet metal substrates used in thin film batteries were wet etched and their surface area was increased in order to increase the discharge capacity and power density of the batteries. To obtain a homogeneous etching pattern, we used a conventional photolithographic process. Homogeneous hemisphere-shaped wells with a diameter of approximately $40\;{\mu}m$ were formed on the surface of the Ti substrate using a photo-etching process with a $20\;{\mu}m{\times}20\;{\mu}m$ square patterned photo mask. All-solid-state thin film cells composed of a Li/Lithium phosphorous oxynitride (Lipon)/$LiCoO_2$ system were fabricated onto the wet etched substrate using a physical vapor deposition method and their performances were compared with those of the cells on a bare substrate. It was found that the discharge capacity of the cells fabricated on wet etched Ti substrate increased by ca. 25% compared to that of the cell fabricated on bare one. High discharge rate was also able to be obtained through the reduction in the internal resistance. However, the cells fabricated on the wet etched substrate exhibited a higher degradation rate with charge-discharge cycling due to the nonuniform step coverage of the thin films, while the cells on the bare substrate demonstrated a good cycling performance.

• New & Renewable Energy
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• v.2 no.2 s.6
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• pp.4-8
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• 2006

Reduction of optical losses in crystalline silicon solar cells by surface modification is one of the most important issues of silicon photovoltaics. Porous Si layers on the front surface of textured Si substrates have been investigated with the aim of improving the optical losses of the solar cells, because an anti-reflection coating and a surface passivation can be obtained simultaneously in one process. We have demonstrated the feasibility of a very efficient porous Si AR layer, prepared by a simple, cost effective, electrochemical etching method. Silicon p-type CZ (100) oriented wafers were textured by anisotropic etching in sodium carbonate solution. Then, the porous Si layer were formed by electrochemical etching in HF solutions. After that, the properties of porous Si in terms of morphology, structure and reflectance are summarized. The surface morphology of porous Si layers were investigated using SEM. The formation of a porous Si layer about $0.1{\mu}m$ thick on the textured silicon wafer result in an effective reflectance coefficient Reff lower than 5% in the wavelength region from 400 to 1000nm. Such a surface modification allows improving the Si solar cell characteristics.

• 한국신재생에너지학회:학술대회논문집
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• 2006.06a
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• pp.183-186
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• 2006

Reduction of optical losses in crystalline silicon solar cells by surface modification is one of the most important issues of silicon photovoltaics. Porous Si layers on the front surface of textured Si substrates have been investigated with the aim of improving the optical losses of the solar cells, because an anti-reflection coating and a surface passivation can be obtained simultaneously in one process. We have demonstrated the feasibility of a very efficient porous Si AR layer, prepared by a simple, cost effective, electrochemical etching method. Silicon p-type CZ (100) oriented wafers were textured by anisotropic etching in sodium carbonate solution. Then, the porous Si layer were formed by electrochemical etching in HF solutions. After that, the properties of porous Si in terms of morphology, structure and reflectance are summarized. The surface morphology of porous Si layers were investigated using SEM. The formation of a porous Si layer about $0.1{\mu}m$ thick on the textured silicon wafer result in an effective reflectance coefficient $R_{eff}$ lower than 5% in the wavelength region from 400 to 1000nm. Such a surface modification allows improving the Si solar cell characteristics.

• Proceedings of the KIEE Conference
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• 2001.07c
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• pp.1890-1892
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• 2001

This paper described on the fabrication of microstructures by DRIE(Deep Reactive Ion Etching). SOI(Si-on-insulator) electric devices with buried cavities are fabricated by SDB technology and electrochemical etch-stop. The cavity was fabricated the upper handling wafer by Si anisotropic etch technique. SDB process was performed to seal the fabricated cavity under vacuum condition at -750 mm Hg. In the SDB process, captured air and moisture inside of the cavities were removed by making channels towards outside. After annealing(1000$^{\circ}C$, 60 min.), the SDB SOI structure was thinned by electrochemical etch-stop. Finally, it was fabricated microstructures by DRIE as well as a accurate thickness control and a good flatness.

• Journal of the Microelectronics and Packaging Society
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• v.29 no.4
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• pp.77-82
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• 2022

During etching process of PCB, the electroplated copper line and seed layer copper have different etching rates and it caused the over etching of copper line as well as undercut of lines. In this research, the effects of etchants composition on copper etching characteristics were investigated. The optimum concentration of hydrogen peroxide and sulfuric acid of etchants were obtained using polarization and OCV (open circuit voltage) analysis for both rolled copper and electroplated copper. The inhibiting effects of different inhibitors were investigated using OCV and ZRA (zero resistance ammeter) analysis. The galvanic current between electroplated copper and seed layer copper were measured using ZRA method. Inhibitors for least galvanic current could be chosen based on galvanic coupling in ZRA analysis.

• Journal of Electrochemical Science and Technology
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• v.12 no.2
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• pp.212-216
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• 2021

We investigated the feasibility of hydrogen storage with electrochemically formed VO₂ nanotubes. The VO₂ nanotubes were fabricated through the anodization of vanadium metal in fluoride ion-containing organic electrolyte followed by an annealing process in an Ar-saturated atmosphere at 673 K for 3 h at a heating rate of 3 K /min. During anodization, the current density significantly increased up to 7.93 mA/cm² for approximately 500 s owing to heat generation, which led to a fast-electrochemical etching reaction of the outermost part of the nanotubes. By controlling the anodization temperature, highly ordered VO₂ nanotubes were grown on the metal substrate without using any binders or adhesives. Furthermore, we demonstrated the hydrogen sorption properties of the anodic VO₂ nanotubes.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.3
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• pp.319-325
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• 2017

Through silicon via (TSV) technology is extensively used in 3D IC integrations. The special structure of the TSV is realized by CMP (Chemically Mechanical Polishing) process with a high Cu removal rate and, low dishing, yielding fine topography without defects. In this study, we investigated the electrochemical behavior of copper slurries with various inhibitors in the Cu CMP process for advanced TSV applications. One of the slurries was carried out for the most promising process with a high removal rate (${\sim}18000{\AA}/Min$ @ 3 psi) and low dishing (${\sim}800{\AA}$), providing good microstructure. The effects of pH value and $H_2O_2$ concentration on the slurry corrosion potential and Cu static etching rate (SER) were also examined. The slurry formula with a pH of 6 and 2% $H_2O_2$, hadthe lowest SER (${\sim}75{\AA}/Min$) and was the best for TSV CMP. A novel Cu TSV CMP process was developed with two CMPs and an additional annealing step after some of the bulk Cu had been removed, effectively improving the condition of the TSV Cu surface and preventing the formation of crack defects by variations in wafer stress during TSV process integration.