• Title/Summary/Keyword: Electrical breakdown voltage

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Mixed-mode simulation of transient characteristics of 4H-SiC DMOSFETs - Impact off the interface changes (Mixde-mode simulation을 이용한 4H-SiC DMOSFETs의 계면상태에서 포획된 전하에 따른 transient 특성 분석)

  • Kang, Min-Seok;Choe, Chang-Yong;Bang, Wook;Kim, Sang-Chul;Kim, Nam-Kyun;Koo, Sang-Mo
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2009.11a
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    • pp.55-55
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    • 2009
  • Silicon Carbide (SiC) is a material with a wide bandgap (3.26eV), a high critical electric field (~2.3MV/cm), a and a high bulk electron mobility (${\sim}900cm^2/Vs$). These electronic properties allow high breakdown voltage, high frequency, and high temperature operation compared to Silicon devices. Although various SiC DMOSFET structures have been reported so far for optimizing performances. the effect of channel dimension on the switching performance of SiC DMOSFETs has not been extensively examined. In this paper, we report the effect of the interface states ($Q_s$) on the transient characteristics of SiC DMOSFETs. The key design parameters for SiC DMOSFETs have been optimized and a physics-based two-dimensional (2-D) mixed device and circuit simulator by Silvaco Inc. has been used to understand the relationship with the switching characteristics. To investigate transient characteristic of the device, mixed-mode simulation has been performed, where the solution of the basic transport equations for the 2-D device structures is directly embedded into the solution procedure for the circuit equations. The result is a low-loss transient characteristic at low $Q_s$. Based on the simulation results, the DMOSFETs exhibit the turn-on time of 10ns at short channel and 9ns at without the interface charges. By reducing $SiO_2/SiC$ interface charge, power losses and switching time also decreases, primarily due to the lowered channel mobilities. As high density interface states can result in increased carrier trapping, or recombination centers or scattering sites. Therefore, the quality of $SiO_2/SiC$ interfaces is important for both static and transient properties of SiC MOSFET devices.

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Effect of Firing Temperature on Microstructure and the Electrical Properties of a ZnO-based Multilayered Chip Type Varistor(MLV) (소성온도에 따른 ZnO계 적층형 칩 바리스터의 미세구조와 전기적 특성의 변화)

  • Kim, Chul-Hong;Kim, Jin-Ho
    • Journal of the Korean Ceramic Society
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    • v.39 no.3
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    • pp.286-293
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    • 2002
  • Microstructure and the electrical porperties of a ZnO-based multilayered chip-type varistor(abbreviated as MLV) with Ag/Pd(7:3) inner electrode have been studied as a function of firing of temperature. At 1100$^{\circ}$C, inner electrode layers began to show nonuniform thickness and small voids, which resulted in significant disappearance of the electrode pattern and delamination at 1100$^{\circ}$C. MLVs fired at 950$^{\circ}$C showed large degradation in leakage current, probably due to incomplete redistribution of liquid and transition metal elements in pyrochlore phase decomposition. Those fired at 1100$^{\circ}$C and above, on the other hand, revealed poor varistor characteristics and their reproductibility, which are though to stem from the deformation of inner electrode pattern, the reaction between electrode materials and ZnO-based ceramics, and the volatilization of $Bi_2O_3$. Throughout the firing temperature range of 950∼1100$^{\circ}$C, capacitance and leakage current increased while breakdown voltage and peak current decreased with the increase of firing temperature, but nonlinear coefficient and clamping ratio kept almost constant at ∼30 and 1.4, respectively. In particular, those fired between 1000$^{\circ}$C and 1050$^{\circ}$C showed stable varistor characteristics with high reproducibility. It seems that Ag/Pd(7:3) alloy is one of the electrode materials applicable to most ZnO-based MLVs incorporating with $Bi_2O_3$ when cofired up to 1050$^{\circ}$C.

Triboelectric Nanogenerator Utilizing Metal-to-Metal Surface Contact (금속-금속 표면 접촉을 활용한 정전 소자)

  • Chung, Jihoon;Heo, Deokjae;Lee, Sangmin
    • Composites Research
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    • v.32 no.6
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    • pp.301-306
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    • 2019
  • Triboelectric nanogenerator (TENG) is one of the energy harvesting methods in spotlight that can convert mechanical energy into electricity. As TENGs produce high electrical output, previous studies have shown TENGs that can power small electronics independently. However, recent studies have reported limitations of TENG due to air breakdown and field emission. In this study, we developed a triboelectric nanogenerator that utilizes the metal-to-metal surface contact to induce ion-enhanced field emission and electron avalanche for electrons to flow directly between two electrodes. The average peak open-circuit voltage of this TENG was measured as 340 V, and average peak closed-circuit current was measured as 10 mA. The electrical output of this TENG has shown different value depending on the surface charge of surface charge generation layer. The TENG developed in this study have produced RMS power of 0.9 mW, which is 2.4 times higher compared to conventional TENGs. The TENG developed in this study can be utilized in charging batteries and capacitors to power portable electronics and sensors independently.

A Comparison Study of Input ESD Protection schemes Utilizing Thyristor and Diode Devices (싸이리스터와 다이오드 소자를 이용하는 입력 ESD 보호방식의 비교 연구)

  • Choi, Jin-Young
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.47 no.4
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    • pp.75-87
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    • 2010
  • For two input-protection schemes suitable for RF ICs utilizing the thyristor and diode protection devices, which can be fabricated in standard CMOS processes, we attempt an in-depth comparison on HBM ESD robustness in terms of lattice heating inside protection devices and peak voltages developed across gate oxides in input buffers, based on DC, mixed-mode transient, and AC analyses utilizing a 2-dimensional device simulator. For this purpose, we construct an equivalent circuit for an input HBM test environment of a CMOS chip equipped with the input ESD protection circuits, which allows mixed-mode transient simulations for various HBM test modes. By executing mixed-mode simulations including up to six active protection devices in a circuit, we attempt a detailed analysis on the problems, which can occur in real tests. In the procedure, we suggest to a recipe to ease the bipolar trigger in the protection devices and figure out that oxide failure in internal circuits is determined by the junction breakdown voltage of the NMOS structure residing in the protection devices. We explain the characteristic differences of two protection schemes as an input ESD protection circuit for RF ICs, and suggest valuable guidelines relating design of the protection devices and circuits.

Characterizations of Sputtered PZT Films on Pt/Ti/Si Substrates. (Pt/Ti/Si 기판위에 형성시킨 PZT박막의 특성)

  • Hwang, Yu-Sang;Baek, Su-Hyeon;Baek, Sang-Hun;Park, Chi-Seon;Ma, Jae-Pyeong;Choe, Jin-Seok;Jeong, Jae-Gyeong;Kim, Yeong-Nam;Jo, Hyeon-Chun
    • Korean Journal of Materials Research
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    • v.4 no.2
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    • pp.143-151
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    • 1994
  • On PT/Ti/Si substrates, PZT thln fllms are deposited at $300^{\circ}C$ by rf magnetron sputtering uslng a $(PbZr_{52}, Ti_{48})O_{3}$ composltc cerarnlc target. To abtaln, the stable phase, perovskltc structure, furnace annealmg techmque had been cmplo:~d In PbO amb~ent for the $550^{\circ}C$-$750^{\circ}C$ temperature ranges. On Pt(250$\AA$)/Ti(500$\AA$)/Si, Pt(1000)$\AA$/Ti(500$\AA$)/Si substrates, effects of Ti layer and Pt thickness are studled. Though thickness of the Pt layer 1s 1000$\AA$). oxygen diffusion is not prevented and accelerated by Ti layer actlng for oxygen sink sites durmg furnace annealing. The upper TI layer 1s transformed Into TIOX by oxyen dlffuslon and lower Ti layer Into silicide with in-diffused Pt. The formation of TiOx layer seems to affect the orlentatton of the PZT layer. Furnace annealed f~lm shows ferroelectr~c and electrical properties wth a remanent polarlzation of 3.3$\mu A /\textrm{cm}^2$, , coerclve fleld of 0.15MV/cm, a=571 (10kHz), leakage current 32.65$\mu A /\textrm{cm}^2$, , breakdown voltage of 0.4OMV/cm.

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Characteristics of Sn-doped β-Ga2O3 single crystals grown by EFG method (EFG 법으로 성장한 β-Ga2O3 단결정의 Sn 도핑 특성 연구)

  • Tae-Wan Je;Su-Bin Park;Hui-Yeon Jang;Su-Min Choi;Mi-Seon Park;Yeon-Suk Jang;Won-Jae Lee;Yun-Gon Moon;Jin-Ki Kang;Yun-Ji Shin;Si-Yong Bae
    • Journal of the Korean Crystal Growth and Crystal Technology
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    • v.33 no.2
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    • pp.83-90
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    • 2023
  • The β-Ga2O3 has the most thermodynamically stable phase, a wide band gap of 4.8~4.9 eV and a high dielectric breakdown voltage of 8MV/cm. Due to such excellent electrical characteristics, this material as a power device material has been attracted much attention. Furthermore, the β-Ga2O3 has easy liquid phase growth method unlike materials such as SiC and GaN. However, since the grown pure β-Ga2O3 single crystal requires the intentionally controlled doping due to a low conductivity to be applied to a power device, the research on doping in β-Ga2O3 single crystal is definitely important. In this study, various source powders of un-doped, Sn 0.05 mol%, Sn 0.1 mol%, Sn 1.5 mol%, Sn 2 mol%, Sn 3 mol%-doped Ga2O3 were prepared by adding different mole ratios of SnO2 powder to Ga2O3 powder, and β-Ga2O3 single crystals were grown by using an edge-defined Film-fed Growth (EFG) method. The crystal direction, crystal quality, optical, and electrical properties of the grown β-Ga2O3 single crystal were analyzed according to the Sn dopant content, and the property variation of β-Ga2O3 single crystal according to the Sn doping were extensively investigated.