• Current Photovoltaic Research
• /
• v.2 no.4
• /
• pp.168-172
• /
• 2014

Under concentrated illuminations, the solar cells show higher efficiencies mainly due to an increase of the open circuit voltage. In this study, InGaP/InGaAs/Ge triple-junction solar cells have been grown by a low pressure metalorganic chemical vapor deposition. Photovoltaic characteristics of the fabricated solar cells are investigated with a class A solar simulator under concentrated illuminations from 1 to 100 suns. Ideally, the open circuit voltage should increase with the current level when maintained at the same temperature. However, the fabricated solar cells show degraded open circuit voltages under high concentrations around 100 suns. This means that the heat sink design is not optimized to keep the cell temperature at $25^{\circ}C$. To demonstrate the thermal degradation, changes of the device performance are investigated with different bonding conditions and heat sink materials.

• 제어로봇시스템학회:학술대회논문집
• /
• 2005.06a
• /
• pp.139-144
• /
• 2005

A rigorous research is underway in our team, for the design and development of high figure of merits (ZT= 1.5${\sim}$2.0) micro-thermoelectric coolers. This paper discusses the fabrication process that we are using for developing the $Sb_2Te_3-Bi_2Te_3$ micro-thermoelectric cooling modules. It describes how to obtain the mechanical properties of the thin film TEC elements and reports the results of an equation-based multiphysics modeling of the micro-TEC modules. In this study the thermoelectric thin films were deposited on Si substrates using co-sputtering method. The physical mechanical properties of the prepared films were measured by nanoindentation testing method while the thermal and electrical properties required for modeling were obtained from existing literature. A finite element model was developed using an equation-based multiphysics modeling by the commercial finite element code FEMLAB. The model was solved for different operating conditions. The temperature and the stress distributions in the P and N elements of the TEC as well as in the metal connector were obtained. The temperature distributions of the system obtained from simulation results showed good agreement with the analytical results existing in literature. In addition, it was found that the maximum stress in the system occurs at the bonding part of the TEC i.e. between the metal connectors and TE elements of the module.

• Journal of the Microelectronics and Packaging Society
• /
• v.22 no.2
• /
• pp.11-19
• /
• 2015

Since CMOS device scaling has stalled, three-dimensional (3-D) integration allows extending Moore's law to ever high density, higher functionality, higher performance, and more diversed materials and devices to be integrated with lower cost. 3-D integration has many benefits such as increased multi-functionality, increased performance, increased data bandwidth, reduced power, small form factor, reduced packaging volume, because it vertically stacks multiple materials, technologies, and functional components such as processor, memory, sensors, logic, analog, and power ICs into one stacked chip. Anticipated applications start with memory, handheld devices, and high-performance computers and especially extend to multifunctional convengence systems such as cloud networking for internet of things, exascale computing for big data server, electrical vehicle system for future automotive, radioactivity safety system, energy harvesting system and, wireless implantable medical system by flexible heterogeneous integrations involving CMOS, MEMS, sensors and photonic circuits. However, heterogeneous integration of different functional devices has many technical challenges owing to various types of size, thickness, and substrate of different functional devices, because they were fabricated by different technologies. This paper describes new 3-D heterogeneous integration technologies of chip self-assembling stacking and 3-D heterogeneous opto-electronics integration, backside TSV fabrication developed by Tohoku University for multifunctional convergence systems. The paper introduce a high speed sensing, highly parallel processing image sensor system comprising a 3-D stacked image sensor with extremely fast signal sensing and processing speed and a 3-D stacked microprocessor with a self-test and self-repair function for autonomous driving assist fabricated by 3-D heterogeneous integration technologies.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2010.10a
• /
• pp.726-729
• /
• 2010

Copper Pillar Tin Bump (CPTB) was investigated for high density chip interconnect technology development, which was prepared by electroplating and electro-less plating methods. Copper pillar tin bumps that have $100{\mu}m$ pitch were introduced with fabrication process using a KM-1250 dry film photoresist (DFR), with copper electroplating for Copper Pillar Bump (CPB) formation firstly, and then tin electro-less plating on it for control oxidation. Electric resistivity and mechanical shear strength measurements were introduced to characterize the oxidation effects and bonding process as a function of thermo-compression. Electrical resistivity increased with increasing oxidation thickness, and shear strength had maximum value with $330^{\circ}C$ and 500 N thermo-compression process. Through the simulation work, it was proved that when the CPTB decreased in its size, it was largely affected by the copper oxidation.

• 한국정보디스플레이학회:학술대회논문집
• /
• 2006.08a
• /
• pp.529-529
• /
• 2006

Several laboratories worldwide have demonstrated the feasibility of producing amorphous silicon thin film transistor (TFT) arrays at temperatures that are sufficiently low to be compatible with flexible foils such as stainless steel or high temperature polyester. These arrays can be used to fabricate flexible high information content display prototypes using a variety of different display technologies. However, several questions must be addressed before this technology can be used for the economic commercial production of displays. These include process optimization and scale-up to address intrinsic electrical instabilities exhibited by these kinds of transistor device, and the development of appropriate techniques for the handling of flexible substrate materials with large coefficients of thermal expansion. The Flexible Display Center at Arizona State University was established in 2004 as a collaboration among industry, a number of Universities, and US Government research laboratories to focus on these issues. The goal of the FDC is to investigate the manufacturing of flexible TFT technology in order to accelerate the commercialization of flexible displays. This presentation will give a brief outline of the FDC's organization and capabilities, and review the status of efforts to fabricate amorphous silicon TFT arrays on flexible foils using a low temperature process. Together with industrial partners, these arrays are being integrated with cholesteric liquid crystal panels, electrophoretic inks, or organic electroluminescent devices to make flexible display prototypes. In addition to an overview of device stability issues, the presentation will include a discussion of challenges peculiar to the use of flexible substrates. A technique has been developed for temporarily bonding flexible substrates to rigid carrier plates so that they may be processed using conventional flat panel display manufacturing equipment. In addition, custom photolithographic equipment has been developed which permits the dynamic compensation of substrate distortions which accumulate at various process steps.

• Proceedings of the KIEE Conference
• /
• 2001.07c
• /
• pp.1921-1923
• /
• 2001

In this work, an array of resistance temperature detector(RTD) was fabricated inside the microchannel in order to investigate in-situ flow characteristics. A rectangular straight microchannel, integrated with RTD's for temperature sensing and a heat source for generating the temperature gradient along the channel. were fabricated with the dimension of $200{\mu}m(W){\times}{\mu}m(D){\times}$48mm(L), while RTD measured precise temperatures at the inside-channel wall. 4" $525{\pm}25{\mu}m$ thick P-type <100> Si wafer was used as a substrate. For the fabrication of RTDs. 5300$\AA$ thick Pt/Ti layer was sputtered on a Pyrex glass wafer. Finally, glass wafer was bonded with Si wafer by anodic bonding, therefore RTD was located inside the microchannel. The temperature distribution inside the fabricated microchannel was obtained from 4 point probe measurements and Dl water is used as a working fluid. Temperature distribution inside the microchannel was measured as a function of mass flow rate and heat flux. As a result, precise temperatures inside the microchannel could be obtained. In conclusion, this novel temperature distribution measurement system will be very useful to the accurate analysis of the flow characteristics in the microchannel.

• Journal of the Korean Ceramic Society
• /
• v.38 no.6
• /
• pp.558-567
• /
• 2001

본 연구에서는 알콕사이드를 전구물질로 하는 졸겔공정을 이용하여 Bi 과잉 12 mol%의 조성인 B $i_4$ $Ti_3$ $O_{12}$ 박막과 B $i_4$ $Ti_{3-x}$T $a_{x}$ $O_{12}$(x=0.1, 0.2, 0.3) 박막을 제조하였다. XPS 분석에 따르면 Ta 치환 x=0.2에서 Bi 4f의 photoemission 곡선이 낮은 결합에너지로 이동하였고 피크 강도가 감소하는 현상이 관측되었다. 이는 x=0.1과 0.2 사이에서 Bi-O 결합이 길어져 인장상태 하에 있었음을 나타내었다. B $i_4$ $Ti_3$ $O_{12}$(BIT) 박막의 유전상수와 유전손실은 100 kHz에서 340, 0.05이었고, B $i_4$ $Ti_{3-x}$T $a_{x}$ $O_{12}$ 박막에서 이들 값은 x=0.1에서 가장 높았으며, 각각 480, 0.13이었다. B $i_4$ $Ti_3$ $O_{12}$ 박막의 잔류분극과 항전계는 1.24$\mu$C/$ extrm{cm}^2$, 31.4 kV/cm 이었으나, Ta 치환 x=0.2에서 이들 값은 각각 19.7$\mu$C/$\textrm{cm}^2$, 49.5 kV/cm 에 이르렀다. 또한, B $i_4$ $Ti_3$ $O_{12}$ 박막의 누설전류 밀도는 ~$10^{-6}$ A/$\textrm{cm}^2$ 정도이었으며, Ta 치환은 누설전류를 감소시켜 Ta 치환 x=0.2 이상에서 BIT 박막에 비해 한 차수 정도 낮아졌다. Ta 치환에 따른 B $i_4$ $Ti_3$ $O_{12}$ 전기 물성에서 변화는 Bi-O 결합에서 관측된 인장상태로의 전이와 연관성이 있었으며, 덧붙여 치환에서 생성된 전자에 의한 정공보상이 이에 영향을 끼쳤다. 정공보상이 이에 영향을 끼쳤다.끼쳤다.

• Journal of the Microelectronics and Packaging Society
• /
• v.15 no.2
• /
• pp.29-36
• /
• 2008

In this paper, mechanical reliability issues of copper through-wafer interconnections are investigated numerically and experimentally. A hermetic wafer level packaging for MEMS devices is developed. Au-Sn eutectic bonding technology is used to achieve hermetic sealing, and the vertical through-hole via filled with electroplated copper for the electrical connection is also used. The MEMS package has the size of $1mm{\times}1mm{\times}700{\mu}m$. The robustness of the package is confirmed by several reliability tests. Several factors which could induce via hole cracking failure are investigated such as thermal expansion mismatch, via etch profile, and copper diffusion phenomenon. Alternative electroplating process is suggested for preventing Cu diffusion and increasing the adhesion performance of the electroplating process. After implementing several improvements, reliability tests were performed, and via hole cracking as well as significant changes in the shear strength were not observed. Helium leak testing indicated that the leak rate of the package meets the requirements of MIL-STD-883F specification.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.43 no.11 s.353
• /
• pp.8-13
• /
• 2006

Recent RF SAW filters are made using a HTCC package with a CSP(chip scale Package) technology. This paper describes a development of a new $1.4{\times}1.1\;and\;2.0{\times}1.4mm$ RF SAW liters made by PCB substrate instead of HTCC package, and this technology can reduce the cost of materials down to 40%. We have investigated the multi-layered PCB substrate structures and raw materials to find out the optimal flip-bonding condition between the $LiTaO_3$ wafer and PCB substrates. Also the optimal materials and processing conditions of epoxy laminating film were found out through the experiments which can reduce the bending moment caused by the difference of the thermal expansion between the PCB substrate and laminating film. The new PCB SAW filter shows good electrical and reliability performances with respect to the present SAW filters.

• Journal of the Korean Society for Aeronautical & Space Sciences
• /
• v.45 no.7
• /
• pp.574-580
• /
• 2017

Static dischargers should be installed on air vehicle to emit a static electricity during flight. Especially, If static electricity is not removed by static discharger on the air vehicle, it makes ionization and corona effect on the edge of antenna and wing. Those phenomenon bring about performance degradation for radio communication and equipment operation. In this paper, the conditions such as climate, air vehicle's speed and frontal area were analyzed to design static dischargers. As a result, the static dischargers would be optimally designed for air vehicles and the performance of the static dischargers can verify according to the functional experiment. Therefore the result of this research will be used to make static discharger installation design for new air vehicle that have different size and mission.