• 제목/요약/키워드: Electrical Die Sorting

검색결과 4건 처리시간 0.023초

웨이퍼 오류 패턴 인식 시뮬레이션 (Wafer Fail Pattern Classification Simulation)

  • 김상진;한영신;이칠기
    • 한국시뮬레이션학회논문지
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    • 제12권3호
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    • pp.13-20
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    • 2003
  • Semiconductor Manufacturing has emerged as one of the most important world industries. Even with the highly automated and precisely monitored facilities used to process the complex manufacturing steps in a near particle free environment, processing variations in wafer fabrication still exist. The causes of these variations may arise from equipment malfunctions, delicate and difficult processing steps, or human mistakes. In this paper, we could specify the cause stage and the cause equipment and take countermeasures at a speed by the conventional method, without depending on the experience and skills of the engineer

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세라믹 소재 초음파 드릴링 가공을 위한 초음파 Horn의 최적 설계에 관한 연구 (Optimal Design of Ultrasonic Horn for Ultrasonic Drilling Processing of Ceramic Material)

  • 차승환;양동호;이상협;이종찬
    • 한국기계가공학회지
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    • 제21권9호
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    • pp.1-11
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    • 2022
  • Recently, there has been continuous technological development in the semiconductor industry, and semiconductor manufacturing technologies are being advanced and highly integrated. For this reason, ceramic material having excellent heat resistance, wear resistance, and conductivity are used as components in semiconductor manufacturing. Among them, the probe card's space transformer is used as ceramic material to prevent electronic signal noise during the electrical die sorting of semiconductor function testing. However, implementing a bulk-type space transformer with a thickness of 5.6 mm or more is challenging, and thus it is produced in a structure with a stacked ceramic film. The stacked space transformer has low productivity because it is difficult to ensure hole clogging and a precise shape. In this research, an ultrasonic horn is designed to manufacture a bulk-type ceramic space transformer through ultrasonic drilling. Vibration characteristics were analyzed according to the ultrasonic horn, and the natural frequency was measured.

FCDD 기반 웨이퍼 빈 맵 상의 결함패턴 탐지 (Detection of Defect Patterns on Wafer Bin Map Using Fully Convolutional Data Description (FCDD) )

  • 장승준;배석주
    • 산업경영시스템학회지
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    • 제46권2호
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    • pp.1-12
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    • 2023
  • To make semiconductor chips, a number of complex semiconductor manufacturing processes are required. Semiconductor chips that have undergone complex processes are subjected to EDS(Electrical Die Sorting) tests to check product quality, and a wafer bin map reflecting the information about the normal and defective chips is created. Defective chips found in the wafer bin map form various patterns, which are called defective patterns, and the defective patterns are a very important clue in determining the cause of defects in the process and design of semiconductors. Therefore, it is desired to automatically and quickly detect defective patterns in the field, and various methods have been proposed to detect defective patterns. Existing methods have considered simple, complex, and new defect patterns, but they had the disadvantage of being unable to provide field engineers the evidence of classification results through deep learning. It is necessary to supplement this and provide detailed information on the size, location, and patterns of the defects. In this paper, we propose an anomaly detection framework that can be explained through FCDD(Fully Convolutional Data Description) trained only with normal data to provide field engineers with details such as detection results of abnormal defect patterns, defect size, and location of defect patterns on wafer bin map. The results are analyzed using open dataset, providing prominent results of the proposed anomaly detection framework.