• 한국전기전자재료학회논문지
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• 제23권12호
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• pp.919-923
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• 2010

Copper pillar tin bump (CPTB) was developed for high density chip interconnect technology. Copper pillar tin bumps that have $100{\mu}m$ pitch were introduced with fabrication process using a KM -1250 dry film photoresist (DFR), copper electroplating method and Sn electro-less plating method. Mechanical shear strength measurements were introduced to characterize the bonding process as a function of thermo-compression. Shear strength has maximum value with $330^{\circ}C$ and 500 N thenno-compression process. Through the simulation work, it was proved that when the copper pillar tin bump decreased in its size, it was largely affected by the copper oxidation.

• 한국전기전자재료학회논문지
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• 제30권5호
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• pp.270-275
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• 2017

Current progress in the development of semiconductor technology in applications involving high electron mobility transistors (HEMT) and power devices is hindered by the lack of adequate ways todissipate heat generated during device operation. Concurrently, electronic devices that use gallium nitride (GaN) substrates do not perform well, because of the poor heat dissipation of the substrate. Suggested alternatives for overcoming these limitations include integration of high thermal conductivity material like diamond near the active device areas. This study will address a critical development in the art of GaN on diamond (GOD) structure by designing for ideal heat dissipation, in order to create apathway with the least thermal resistance and to improve the overall ease of integrating diamond heat spreaders into future electronic devices. This research has been carried out by means of heat transfer simulation, which has been successfully demonstrated by a finite-element method.

• 전기학회논문지
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• 제57권10호
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• pp.1822-1828
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• 2008

This paper presents design parameter calculation methodology and its realization to construction for the 10/350${\mu}s$ lightning impulse current generator(ICG) modelled as double exponential function waveform with characteristic parameters ${\alpha},{\beta}$. Matlab internal function, "fzero" was applied to find ${\lambda}={\alpha}/{\beta}$ which is solution of nonlinear equation linearly related with two wave parameter $T_1$ and $T_2$. The calculation results for 10/350${\mu}s$ lightning impulse current show very good accuracy with error less 0.03%. Two type of 10/350${\mu}s$ ICGs based on the calculated design circuit parameters were fabricated by considering the load variation. One is applicable to the MOV based Surge protective device(SPD) for less 15 kA and the other is to test small resistive devices such as spark gap arrester and bonding device with maximum current capability 30 kA. The tested waveforms show error within 10% in comparison with the designed estimation and the waveform tolerance recommended in the IEC 61643-1 and IEC 60060-1.

• 한국전기전자재료학회논문지
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• 제13권6호
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• pp.514-519
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• 2000

This paper describes on the temperature characteristics of a SDB(silicon-wafer direct bonding) SOI(silicon-on-insulator) Hall sensor. Using the buried oxide $SiO_2$as a dielectrical isolation layer a SDB SOI Hall sensor without pn junction has been fabricated on the Si/ $SiO_2$/Si structure. The Hall voltage and the sensitivity of the implemented SOI Hall sensor show good linearity with respect to the applied magnetic flux density and supplied current. In the temperature range of 25 to 30$0^{\circ}C$ the shifts of TCO(temperature coefficient of the offset voltage) and TCS(temperature coefficient of the product sensitivity) are less than $\pm$6.7$\times$10$_{-3}$ and $\pm$8.2$\times$10$_{-4}$$^{\circ}C$ respectively. These results indicate that the SDB SOI structure has potential for the development of a silicon Hall sensor with a high-sensitivity and high-temperature operation.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2001년도 하계학술대회 논문집
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• pp.435-438
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• 2001

Thin films of vanadium oxide(VO$\sub$x/) have been deposited by r.f. magnetron sputtering from V$_2$O$\sub$5/ target in gas mixture of argon and oxygen. The oxygen/(oxygen+argon) partial pressure ratio is changed from 0% to 8%. Crystal structure, chemical composition and bonding properties of films sputter-deposited under different oxygen gas pressures are characterized through XRO, XPS, RBS and FTIR measurements. All the films prepared below 8% O$_2$ are amorphous, and those prepared without oxygen are gray indicating the presence of V$_2$O$\sub$$_4$/ phase in the films. V$_2$O$\sub$5/ and lower oxides co-exist in sputter-deposited films and as the oxygen partial pressure is increased the films become more stoichiometric V$_2$O$\sub$5/. The increase of O/V ratio with increasing oxygen gas pressure is attributed to the partial filling of oxygen vacancies through diffusion. It is observed that the oxygen atoms. located on the V-O plane of V$_2$O$\sub$5/ layer participate more readily in the oxidation process.

• Journal of the Optical Society of Korea
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• 제16권1호
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• pp.1-5
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• 2012

This paper describes a 150-Mb/s monolithic optical receiver for plastic optical fiber link using a standard CMOS technology. The receiver integrates a photodiode using an N-well/P-substrate junction, a pre amplifier, a post amplifier, and an output driver. The size, PN-junction type, and the number of metal fingers of the photodiode are optimized to meet the link requirements. The N-well/P-substrate photodiode has a 200-${\mu}m$ by 200-${\mu}m$ optical window, 0.1-A/W responsivity, 7.6-pF junction capacitance and 113-MHz bandwidth. The monolithic receiver can successfully convert 150-Mb/s optical signal into digital data through up to 30-m plastic optical fiber link with -10.4 dBm of optical sensitivity. The receiver occupies 0.56-$mm^2$ area including electrostatic discharge protection diodes and bonding pads. To reduce unnecessary power consumption when the light is not over threshold or not modulating, a simple light detector and a signal detector are introduced. In active mode, the receiver core consumes 5.8-mA DC currents at 150-Mb/s data rate from a single 3.3 V supply, while consumes only $120{\mu}W$ in the sleep mode.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2002년도 하계학술대회 논문집
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• pp.310-313
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• 2002

Structures obtained with a direct boning of two FZ silicon wafers joined in such a way that a smooth surface of one wafer was attached to the grooved surface of the other were studied. A square net of grooves was made with a conventional photo lithography process. After high temperature annealing the appearance of voids and the rearrangement of structural defects were observed with X-ray diffraction topography techniques. It was shown that the formation of void free grooved boundaries was feasible. In the cases when particulate contamination was prevented, the voids appeared in the grooved structures could be eliminated with annealing. Since it was found that the flattening was accompanied with plastic deformation, this deformation was suggested to be intensively involved in the process of void removal. A model was proposed explaining the interaction between the structural defects resulted in "a dissolution" of cavities. The described processes may occur in grooved as well as in smooth structures, but there are the former that allow to manage air traps and undesirable excess of dislocation density. Grooves can be paths for air leave. According to the established mechanisms, if not outdone, the dislocations form local defect arrangements at the grooves permitting the substantial reduction in defect density over the remainder of the interfacial area.

• 한국전기전자재료학회논문지
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• 제19권12호
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• pp.1078-1084
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• 2006

Impurity contamination induced by $CF_4\;and\;HBr/Cl_2/O_2$ plasma etching on Si surface was examined by using surface spectroscopes. XPS(x-ray photoelectron spectroscopy) surface analysis showed that F of 0.4 at % exists in the surface layer in the form of Si-F bonding but Br and Cl are below the detection limit $(0.1{\sim}1.0%)$ of the spectroscope. Static-SIMS(secondary ion mass spectrometry) surface analysis showed that the etched Si surface was contaminated with etching gas elements such as H, F, Cl and Br, and they existed to the depth of about $20{\sim}40nm$. The etched Si surface was treated with three different methods that were HF dip, thermal oxidation followed by HF dip and oxygen-plasma oxidation followed by HF dip. They showed an effect in reducing the impurity contamination and the oxygen-plasma oxidation followed by HF dipping method appears to be a little bit more effective.

• 한국전기전자재료학회논문지
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• 제15권11호
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• pp.958-962
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• 2002

This paper reports on the fabrication of free-standing microstructures by DRIE (deep reactive ion etching). SOI (Si-on-insulator) structures with buried cavities are fabricated by SDB (Si-wafer direct bonding) technology and electrochemical etch-stop. The cavity was formed the upper handling wafer by Si anisotropic etch technique. SDB process was performed to seal the formed cavity under vacuum condition at -760 mmHg. In the SDB process, captured air and moisture inside of the cavities were removed by making channels towards outside. After annealing (100$0^{\circ}C$, 60 min.), the SDB SOI structure with a accurate thickness and a good roughness was thinned by electrochemical etch-stop in TMAH solution. Finally, it was fabricated free-standing microstructures by DRIE. This result indicates that the fabrication technology of free-standing microstructures by combination SDB, electrochemical etch-stop and DRIE provides a powerful and versatile alternative process for high-performance bulk micromachining in MEMS fields.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2000년도 영호남학술대회 논문집
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• pp.29-33
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• 2000

This paper describes on the temperature characteristics of a SDB(silicon-wafer direct bonding) SOI(silicon-on-insulator) Hall sensor. Using the buried oxide $SiO_2$ as a dielectrical isolation layer, a SDB SOI Hall sensor without pn junction isolation has been fabricated on the Si/$SiO_2$/Si structure. The Hall voltage and the sensitivity of the implemented SOI Hall sensor show good linearity with respect to the applied magnetic flux density and supplied current. In the temperature range of 25 to $300^{\circ}C$, the shifts of TCO(temperature coefficient of the offset voltage) and TCS(temperature coefficient of the product sensitivity) are less than ${\pm}6.7{\times}10^{-3}/^{\circ}C$ and ${\pm}8.2{\times}10^{-4}/^{\circ}C$, respectively. These results indicate that the SDB SOI structure has potential for the development of a silicon Hall sensor with a high-sensitivity and high-temperature operation.