• Journal of Korea Society of Digital Industry and Information Management
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• v.9 no.1
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• pp.111-118
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• 2013

This paper presents implementation of Air protocol analyzer and physical layer design algorithm. The analyzer is a measurement system providing real-time analysis of wireless signals between User Equipment (UE) and Node-B. The implemented system proposed in this paper consists of Digital Signal Processors (DSPs) and Field Programmable Gate Arrays (FPGAs). The waveform of Wideband Code Division Multiple Access (WCDMA) has been selected for verification of the proposed system. We designed the analyzer using equalizer algorithm and rake-receiver algorithm. Among various algorithms of designing the equalizer, we have chosen Linear Minimum Mean Square Error (LMMSE) equalizer that uses the inverse of channel matrix. Since the LMMSE equalizer uses the inverse channel matrix, it suffers from a large amount of computational load, while it outperforms most conventional equalizers. In this paper, we introduce an efficient procedure of reducing the computational load required by LMMSE equalizer-based receiver.

• Journal of the Korean Institute of Telematics and Electronics
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• v.20 no.4
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• pp.10-15
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• 1983

In this paper effective methods of demodulation and equalization in a 9600 bps modem have been studied. To reduce the number of multiplications required per symbol in demodula-tion, the method of using a decimation filter is presented. In the equalizer the optimum step size and the steady state mean-squared error (MSE) are obtained from computer simulation results. The performance of the first-order carrier phase tracking loop is compared with that of the second-order loop when carrier frequency offset exists. In addition, the finite word length effects in the equalizer are studied.

• Journal of Power Electronics
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• v.16 no.4
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• pp.1469-1482
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• 2016

In hybrid energy storage systems, supercapacitors are usually connected in series to meet the required voltage levels. Equalizers are effective in prolonging the life of hybrid energy storage systems because they eliminate the voltage imbalance on cells. This study proposes a modularized equalizer, which is based on a combination of a half-bridge inverter, an inductor, and two auxiliary capacitors. The proposed equalizer inherits the advantages of inductor-based equalization systems, but it also offers unique merits, such as low switching losses and an easy-to-use control algorithm. The zero-voltage switching scheme is analyzed, and the power model is established. A fixed-frequency operation strategy is proposed to simplify the control and lower the cost. The switching patterns and conditions for zero-voltage switching are discussed. Simulation results based on PSIM are presented to verify the validity of the proposed equalizer. An equalization test for two supercapacitor cells is performed. An experimental hybrid energy storage system, which consists of batteries and supercapacitors, is established to verify the performance of the proposed equalizer. The analysis, simulation results, and experimental results are in good agreement, thus indicating that the circuit is practical.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.39A no.11
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• pp.645-651
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• 2014

For blind equalization, we propose a method of updating an equalizer, which generates an error from selectively applying a transmitted symbol constellation and that of induced equivalently from the transmitted symbol constellation and updates the equalizer by using this error. The proposed method, by selectively using the symbol constellation effective for improvement of symbol estimation accuracy and that of effective for improvement of error performance, showed that it is possible to improve the error performance at the same time to open the eye diagram of equalizer output quickly. As a criterion applying the symbol constellation, we used the dispersion of symbol points of equalizer output. In addition, to increase the accuracy of updating an equalizer the error was controlled by using current and previous dispersions. By simulation, under multipath channel with additive noise, we verified the equalization performance of the proposed method for 64-QAM.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.7
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• pp.52-58
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• 2013

This paper proposes an adaptive algorithm based on a method of dynamic error signal generation suitable for signal state by examining the equalizer output signal in blind equalization. In the proposed method, it estimates the error signals using single modulus and multiple modulus each effective to the early stage of equalization or steady-state, and it generates a new error signal from the two error estimates. Two equalizer structures are implemented and their performances are compared: 1-equalizer structure that generates a new error signal by combining the two error estimates weightedly and updates the equalizer using this, and 2-equalizer structure that updates two equalizers respectively depending on the weights of the two error signals. In the proposed method, as the error signals were generated optimally before and after the initial convergence respectively, it was confirmed by computer simulations that the equalizer was updated effectively.

• Journal of IKEEE
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• v.14 no.1
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• pp.33-39
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• 2010

In this paper, a 5Gb/s receiver with an adaptive equalizer for serial link interfaces is proposed. For effective gain control, a least-mean-square (LMS) algorithm was implemented with two internal signals of slicers instead of output node of an equalizing filter. The scheme does not affect on a bandwidth of the equalizing filter. It also can be implemented without passive filter and it saves chip area and power consumption since two internal signals of slicers have a similar DC magnitude. The proposed adaptive equalizer can compensate up to 25dB and operate in various environments, which are 15m shield-twisted pair (STP) cable for DisplayPort and FR-4 traces for backplane. This work is implemented in $0.18-{\mu}m$ 1-poly 4-metal CMOS technology and occupies $200{\times}300{\mu}m^2$. Measurement results show only 6mW small power consumption and 2Gbps operating range with fabricated chip. The equalizer is expected to satisfy up to 5Gbps operating range if stable varactor(RF) is supported by foundry process.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.15 no.10 s.89
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• pp.996-1004
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• 2004

1-Dimensional Cluster-Based Sequence Equalizer(1-D CBSE) lessens computational load, compared with the classic maximum likelihood sequence estimation(MLSE) equalizers, and has the superiority in the nonlinear channels. In this paper, we proposed an algorithm of searching for optimal training sequence that estimates the cluster centers instead of time-varying multipath fading channel estimation. The proposed equalizer not only resolved the problems in 1-D CBSE but also improved the bandwidth efficiency using the shorten length of taming sequence to improve bandwidth efficiency. In experiments, the superiority of the new method is demonstrated by comparing conventional 1-D CBSE and related analysis.

• Journal of information and communication convergence engineering
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• v.8 no.6
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• pp.687-689
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• 2010

In this paper, the equalization for frequency slope of path loss in Multi-Band(MB) OFDM UWB is proposed. The path loss of a signal is proportionate to the square of the signal's frequency. So, the received signal amplitudes of OFDM subcarrier can be different up to 3dB when MB-OFDM occupies bandwidth over 1.5GHz. The differences of subcarrier-amplitudes make an effective of 0.3 bit reduction of soft decision bits of viterbi decoder, and when the effective of 0.3 bit reduction can cause 0.5dB SNR degradation. This paper proposes two modem architectures which compensate for the degraded subcarrier by multiplying the reciprocal of degraded values in analog or digital domain. It is shown that, for the proposed architecture applied to MB-OFDM UWB, the performance improvements up to 0.5dB can be obtained over the conventional uncompensated receiver architecture.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.3 no.1 s.4
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• pp.109-116
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• 2004

The signal in wireless multi-path channel is affected by fading and ISI because of high data rate transmission, so the signal has the high error rate. The present modulation and demodulation method of DSRC system can not expect sufficient for providing data service over 1 Mbps, so the channel equalization and advanced modulation and demodulation methods are required. OFDM method is generally Inon as an effective technique for high data rate transmission system, since it can prevent ISI by inserting a guard interval. However, a guard interval longer than channel delay spread has to be used in each OFDM symbol period, thus resulting a considerable loss in the efficiency of channel utilization. Therefore the equalizer is necessary to cancel ISI to accommodate advanced ISI service with higher bit rate and longer channel delay spread condition. In this thesis, the channel equalizer for the OFDM-DSRC system was designed and its performance in a multi-path fading environment was evaluated with computer simulation. As a result, the performance of Pseudo LMMSE equalizer for the OFDM-DSRC has been improved comparing with LS equalizer at higher bit rate transmission system.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.2
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• pp.28-33
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• 2008

This paper presents a continuous-time equalizer adopting a clock loss tracking technique for digital display interface. This technique uses bottom hold circuit to detect the incoming clock loss. The generated loss signal is directly fed to equalizer filters, building adaptive feed-forward loops which contribute the stability of the system. The design was done in $0.18{\mu}m$ CMOS technology. Experimental results summarize that eye-width of minimum 0.7UI is achieved until -33dB channel loss at 1.65Gbps. The average power consumption of the equalizer is a maximum 10mW, a very low value in comparison to those of previous researches, and the effective area is $0.127mm^2$.