• The Journal of the Korea Contents Association
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• v.7 no.11
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• pp.102-110
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• 2007

In this paper, a portable RFID reader which operated in 900MHz UHF band is designed and fabricated and the characteristics of the manufactured portable RFID reader is analyzed through measurement. Analysis of measurements results is achieved based on EPC Class 0 standards that proposed by EPC Global. The proposed RFID reader communicate with tags about 11kbps speed, and have 20 dBm for its maximum RF output power. The proposed portable RFID reader can recognize maximum 68 tags per second, and when reader's output power is 20 dBms, maximum recognition distance is 30cm. And the total size of implemented RFID reader is $71mm{\times}55mm$, that is the maximum 90%, minimum 14% reduced size compared with marketed product.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.3A
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• pp.360-367
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• 2006

In this paper, we designed a digital codec of an RFID tag for EPC global generation 2 class 1. There are a large number of studies on RRD standard and anti-collision algorithm but few studies on the design of digital parts of the RFID tag itself. For this reason, we studied and designed the digital codec hardware for EPC global generation 2 class 1 tag. The purpose of this paper is not to improve former studies but to present the hardware architecture, an estimation of hardware size and power consumption of digital part of the RFID tag. Results are synthesized using Synopsys with a 0.35um standard cell library. The hardware size is estimated to be 111640 equivalent inverters and dynamic power is estimated to be 10.4uW. It can be improved through full-custom design, but we designed using a standard cell library because it is faster and more efficient in the verification and the estimation of the design.

• The Journal of the Korea Contents Association
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• v.8 no.3
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• pp.18-24
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• 2008

This paper analyzed Air Interface of EPCglobal's Class-0 that is UHF band protocol among radio environment protocol standard that is used to RFID system. And embodied prescribed anticollision algorithm in protocol. Also, the improved anticollision algorithm for the Class-0 protocol is proposed and performances of anticollision algorithm are compared. Result that compare performance of standard algorithm through simulation with improved algorithm, improved Class-0 algorithm when is tag number 100, reduced 8%, and when is tag number 1000, 12.2%. According as tag number increases, total realization time of improved algorithm decreased more gradually better than prescribed algorithm. Therefore, the improved anticollision algorithm proposed in this paper is advanced method improving the performance of tag recognition in the RFID system and Ubiquitous sensor network.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.7B
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• pp.1081-1090
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• 2010

$0.18{\mu}m$ CMOS UHF RFID tag frontend is presented in this paper. Several key components are highlighted: the voltage multiplier based on the threshold voltage terminated circuit, the demodulator using current mode, and the clock generator. For standard compliance, all designed components are under the EPC Global Class-1 Generation-2 UHF RFID protocol. Backscatter modulation uses the pulse width modulation scheme. Overall performance of the proposed tag chip was verified with the evaluation board. Prototype Tag Chip dimension is neary 0.77mm2 ; According to the simulation results, the reader can successfully interrogate the tag within 1.5m. where the tag consumes the power about $71{\mu}W$.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.46 no.11
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• pp.12-17
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• 2009

This paper presents a tag emulator for a UHF band RFID system. The tag emulator supports the 1800-6C and EPC global class 1 generation 2 standards. The transmitted signal from a reader is generated using the PIE coding and ASK modulation methods. Signals of a tag are from the FM0 coding and ASK modulation methods. The ARM7 processor carries out the overall control of the system and signal analysis of incoming data. The verification of the tag emulator employs the application platform implemented in C++. Users can define parameter values for protocol during the application run. The tag emulator presented in this paper allows evaluating various design alternatives of the target RFID system in real applications.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.8A
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• pp.847-857
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• 2007

For the implementation of a RFID system, an anti-collision algorithm is required to identify multiple tags within the range of a RFID Reader. A Bit-by-Bit algorithm is defined by Auto ID Class 0. In this paper, we propose a SBBB(Stack Bit-by-Bit) algorithm. The SBBB algorithm save the collision position and makes a query using the saved data. SBBB improve the efficiency of collision resolution. We show the performance of the SBBB algorithm by simulation. The performance of the proposed algorithm is higher than that of BBB algorithm. Especially, the more each tag bit streams are the duplicate, the higher performance is.

• Proceedings of the KIEE Conference
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• 2007.10a
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• pp.191-192
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• 2007

This paper presents a 900MHz fractional-N frequency synthesizer for radio frequency identification (RFID) reader using $0.18{\mu}m$ standard CMOS process. The IC meets the EPC Class-1 Generation-2 and ISO-18000 Type-C standards. To minimize VCO pulling, the 900MHz VCO is generated by a 1.8GHz VCO followed by a frequency divider. The settling time of the synthesizer is less than $20{\mu}m$. The frequency synthesizer achieves the phase noise of -105.6dBc/Hz at 200kHz offset. The frequency synthesizer occupies an area of $1.8{\times}0.99mm^2$, and dissipates 8mA from a low supply voltage of 1.8V.