• 제목/요약/키워드: Dynamic voltage converter

검색결과 254건 처리시간 0.028초

풀-브릿지 영전압 영전류 컨버터의 소신호 모델링 (Small-signal Analysis of the Full bridge ZVZCS converter)

  • 최항석;조보형
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 1999년도 하계학술대회 논문집 F
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    • pp.2518-2521
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    • 1999
  • A Full-bridge zero-voltage zero-current switching (ZVZCS) converter using transformer auxiliary winding is analyzed. A complete small-signal model for the control scheme is developed. The propoed model is accurate up to half the switching frequency. The dynamic characteristics are compared with those of the zero-voltage switching converter and buck converter. Model predictions are confirmed by experimental measurements.

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관성측정장치의 아날로그 재평형 루프에 따르는 A-D 변환기의 설계에 관한 연구 (A study on the design of the A-D converter for analog rebalance loop in INS)

  • 안영석;김종웅;이의행
    • 제어로봇시스템학회:학술대회논문집
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    • 제어로봇시스템학회 1987년도 한국자동제어학술회의논문집; 한국과학기술대학, 충남; 16-17 Oct. 1987
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    • pp.522-527
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    • 1987
  • This paper describes the hardware of analog-to-digital converter to process the rate output of analog servo loop for the gyro rebalance of INS. The analog-to-digital converter is designed by voltage-to-frequency method which is generally used in INS, and this scheme fits well into the strapdown INS that requires the wide dynamic range and linearity. The output of the designed voltage to frequency converter is tested by computer through the counter and all the factors which affect the performance are considered.

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Controller Optimization Algorithm for a 12-pulse Voltage Source Converter based HVDC System

  • Agarwal, Ruchi;Singh, Sanjeev
    • Journal of Electrical Engineering and Technology
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    • 제12권2호
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    • pp.643-653
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    • 2017
  • The paper presents controller optimization algorithm for a 12-pulse voltage source converter (VSC) based high voltage direct current (HVDC) system. To get an optimum algorithm, three methods namely conventional-Zeigler-Nichols, linear-golden section search (GSS) and stochastic-particle swarm optimization (PSO) are applied to control of 12 pulse VSC based HVDC system and simulation results are presented to show the best among the three. The performance results are obtained under various dynamic conditions such as load perturbation, non-linear load condition, and voltage sag, tapped load fault at points-of-common coupling (PCC) and single-line-to ground (SLG) fault at input AC mains. The conventional GSS and PSO algorithm are modified to enhance their performances under dynamic conditions. The results of this study show that modified particle swarm optimization provides the best results in terms of quick response to the dynamic conditions as compared to other optimization methods.

동적 전류분담 인덕터를 이용한 ZVT 풀 브리지 컨버터의 병렬 운전 (The Parallel Operation of ZVT-Full Bridge Converter with Dynamic Current Shared Inductor)

  • 김용
    • 조명전기설비학회논문지
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    • 제16권4호
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    • pp.15-21
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    • 2002
  • 본 논문에서는 동적 전류분담 인덕터를 이용한 ZVT 풀 브리지 DC/DC 컨버터의 병렬운전 특성을 해석하였다. 기존의 경우 CT(Current Transformer)를 사용하여 각 단위 컨버터 전류의 크기를 감지하여, 제어회로에서 각 컨버터에 균등한 전류 배분을 하는 방법을 사용하였으나, 본 연구에서는 동적 전류분담 인덕터를 사용함으로써 병렬운전하는 두 대의 풀 브리지 컨버터의 전류분배를 위한 제어회로를 비교적 단순하게 하였다. 동시에 ZVT회로를 이용하여 컨버터의 효율을 향상시켰으며 스위칭소자로서 IGBT를 사용하여 2[㎾]급 시작품을 제작, 50[KHz]에서 실험하였다.

절연형 이중 강압 직류-직류 컨버터의 동특성 해석 및 제어회로 설계 (Dynamic Analysis and Control Circuit Design of Isolated Double Step-Down DC-DC Converter)

  • 하헌철;김한상;최병조
    • 전력전자학회:학술대회논문집
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    • 전력전자학회 2015년도 전력전자학술대회 논문집
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    • pp.229-230
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    • 2015
  • This paper presents practical details about control-loop design and dynamic analysis for a voltage-mode controlled isolated double step-down DC-DC converter. Graphical loop gain method is used to design the feedback compensation and analyze the closed-loop performance of isolated double step-down DC-DC converter. The results of the control design and closed-loop analysis are validated by experiments on a prototype converter.

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Fuzzy Controlled ZVS Asymmetrical PWM Full-bridge DC-DC Converter for Constant load High Power Applications

  • Marikkannan., A;Manikandan., B.V
    • Journal of Electrical Engineering and Technology
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    • 제12권3호
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    • pp.1235-1244
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    • 2017
  • This paper proposes a fuzzy logic controlled new topology of high voltage gain zero voltage switching (ZVS) asymmetrical PWM full-bridge DC-DC boost converter for constant load and high power applications. The APWM full-bridge stage provides high voltage gain and soft-switching characteristics increase the efficiency and reduce the switching losses. Fuzzy logic controller (FLC) improves the performance and dynamic characteristics of the proposed converter. A comparison with a classical proportional-integral (PI) controller demonstrates the high performances of the proposed technique in terms of effective output voltage regulation under different operating conditions. Simulation is done by integrating two different simulation platforms $PSIM^{(R)}$ and $Matlab^{(R)}/Simulink^{(R)}$ by using SimCoupler tool of $PSIM^{(R)}$. Experimental results using 120W load have been provided to validate the results.

스위치 전도 손실을 개선한 인터리브 DC-DC 벅-부스트 컨버터 설계 (A Design of Interleaved DC-DC Buck-boost Converter with Improved Conduction Loss of Switch)

  • 이주영;주환규;이현덕;양일석;구용서
    • 전기전자학회논문지
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    • 제14권3호
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    • pp.250-255
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    • 2010
  • 본 논문에서는 DTMOS(Dynamic Threshold voltage MOSFET) 스위칭 소자를 사용한 인터리브 방식의 전원제어 장치(PMIC)를 제안하였다. 휴대기기에 필요한 높은 출력 전압과 낮은 출력 전압을 제공하기 위하여 벅-부스트 컨버터를 사용하였다. 또한, 높은 출력 전류에서 고 전력 효율을 얻기 위하여 PWM(Pulse Width Modulation) 제어 방식을 사용하였다. 낮은 온-저항을 갖는 DTMOS를 사용하여 도통 손실을 감소시켰으며 인터리브 방식을 사용하여 출력 리플을 감소시켰다. 1mA 이하의 대기모드에서도 높은 효율을 구현하기 위하여 LDO를 설계하였다.

Dynamic Threshold MOS 스위치를 사용한 고효율 DC-DC Converter 설계 (The design of the high efficiency DC-DC Converter with Dynamic Threshold MOS switch)

  • 하가산;구용서;손정만;권종기;정준모
    • 전기전자학회논문지
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    • 제12권3호
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    • pp.176-183
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    • 2008
  • 본 논문에서는 DTMOS(Dynamic Threshold voltage MOSFET) 스위칭 소자를 사용한 고 효율 전원 제어 장치 (PMIC)를 제안하였다. 높은 출력 전류에서 고 전력 효율을 얻기 위하여 PWM(Pulse Width Modulation) 제어 방식을 사용하여 PMIC를 구현하였으며, 낮은 온 저항을 갖는 DTMOS를 설계하여 도통 손실을 감소시켰다. 벅 컨버터(Buck converter) 제어 회로는 PWM 제어회로로 되어 있으며, 삼각파 발생기(Saw-tooth generator), 밴드갭기준 전압 회로(Band-gap reference circuit), 오차 증폭기(Error amplifier), 비교기(Comparator circuit)가 하나의 블록으로 구성되어 있다. 삼각파 발생기는 그라운드부터 전원 전압(Vdd:3.3V)까지 출력 진폭 범위를 갖는 1.2MHz 발진 주파수를 가지며, 비교기는 2단 연산 증폭기로 설계되었다. 그리고 오차 증폭기는 70dB의 DC gain과 $64^{\circ}$ 위상 여유를 갖도록 설계하였다. Voltage-mode PWM 제어 회로와 낮은 온 저항을 스위칭 소자로 사용하여 구현한 DC-DC converter는 100mA 출력 전류에서 95%의 효율을 구현하였으며, 1mA이하의 대기모드에서도 높은 효율을 구현하기 위하여 LDO를 설계하였다.

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Voltage control of three phase rectifier with current-controlled voltage type converter

  • 우명호;정승기
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 1991년도 추계학술대회 논문집 학회본부
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    • pp.207-209
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    • 1991
  • This paper deals with voltage control method of PWM rectifier using current-controlled voltage type converter. A linearized model of the current-controlled rectifier is derived, which is used to examine the effect of controller gains to its dynamic responses. Through the simulation, it is shown that the proposed model is generally valid, which is confirmed by experimental results.

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Sampled-Data Modeling and Dynamic Behavior Analysis of Peak Current-Mode Controlled Flyback Converter with Ramp Compensation

  • Zhou, Shuhan;Zhou, Guohua;Zeng, Shaohuan;Xu, Shungang;Cao, Taiqiang
    • Journal of Power Electronics
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    • 제19권1호
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    • pp.190-200
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    • 2019
  • The flyback converter, which can be regarded as a nonlinear time-varying system, has complex dynamics and nonlinear behaviors. These phenomena can affect the stability of the converter. To simplify the modeling process and retain the information of the output capacitor branch, a special sampled-data model of a peak current-mode (PCM) controlled flyback converter is established in this paper. Based on this, its dynamic behaviors are analyzed, which provides guidance for designing the circuit parameters of the converter. With the critical stability boundary equation derived by a Jacobian matrix, the stable operation range with a varied output capacitor, proportional coefficient of error the amplifier, input voltage, reference voltage and slope of the compensation ramp of a PCM controlled flyback converter are investigated in detail. Research results show that the duty ratio should be less than 0.5 for a PCM controlled flyback converter without ramp compensation to operate in a stable state. The stability regions in the parameter space between the output capacitor and the proportional coefficient of the error amplifier are enlarged by increasing the input voltage or by decreasing the reference voltage. Furthermore, the ramp compensation also can extend to the stable region. Finally, time-domain simulations and experimental results are presented to verify the theoretical analysis results.