• 제목/요약/키워드: Dynamic Dissipation

검색결과 341건 처리시간 0.028초

On the Large Eddy Simulation of High Prandtl Number Scalar Transport Using Dynamic Subgrid-Scale Model

  • Na, Yang
    • Journal of Mechanical Science and Technology
    • /
    • 제18권1호
    • /
    • pp.173-182
    • /
    • 2004
  • The present study has focused on numerical investigation on the flame structure, flame lift-off and stabilization in the partially premixed turbulent lifted jet flames. Since the lifted jet flames have the partially premixed nature in the flow region between nozzle exit and flame base, level set approach is applied to simulate the partially premixed turbulent lifted jet flames for various fuel jet velocities and co-flow velocities. The flame stabilization mechanism and the flame structure near flame base are presented in detail. The predicted lift-off heights are compared with the measured ones.

Shift Characteristics Analysis and Smooth Shift for an Automatic Power Transmission

  • Jeong, Heon-Sul;Lee, Kyo-Ill
    • Journal of Mechanical Science and Technology
    • /
    • 제14권5호
    • /
    • pp.499-507
    • /
    • 2000
  • Smooth shift is one of the key issues in automatic power transmission control systems. However, the torque sensors are too expensive to be used in shift controllers on production vehicles. In order to provide a basic strategy for smooth shifting by using RPM sensors only and in order to accomplish the shift within a designated time, this paper studies detailed characteristics of the smooth shift for clutch-to-clutch shift mechanism. A desired trajectory of slip speed is proposed for smooth acceleration shift defined in this paper. Also the clutch torque needed to achieve this trajectory is derived, and it may be used as a open loop shift control law.

  • PDF

12 비트 100 MHz CMOS 디지털/아날로그 변환기의 설계 (Design of A 12-Bit 100-MHz CMOS Digital-to-Analog Converter)

  • 이주상;최일훈;김규현;유상대
    • 대한전기학회:학술대회논문집
    • /
    • 대한전기학회 2002년도 합동 추계학술대회 논문집 정보 및 제어부문
    • /
    • pp.609-612
    • /
    • 2002
  • In this paper, a 12-bit 100-MHz CMOS current steering digital-to-analog converter is designed. In the D/A converter, a driver circuit using a dynamic latch is implemented to obtain low glitch and thermometer decoder is used for low DNL errors, guaranteed monotonicity, reduced stitching noise. And a threshold voltage-compensated current source. The D/A converter is designed with 0.35-$\mu m$ CMOS technology at 3.3 V power supply and simulated with HSPICE. The maximum power dissipation of the designed DAC is 143 mW.

  • PDF

연소기에서의 다단 저 NOx 버너의 수치 및 실험적 연구 (Numerical & Experimental Study For Burner of Low NOx Formation of Multi-Stage In a Combustor)

  • 최윤기;강경태;김용모
    • 한국연소학회:학술대회논문집
    • /
    • 대한연소학회 2003년도 제27회 KOSCO SYMPOSIUM 논문집
    • /
    • pp.65-74
    • /
    • 2003
  • Air pollution included Nitric Oxide(NOx) from heating boilers is increased by pursuing better life. Development of low NOx emission boiler is strongly needed. However commercial burner for heating boiler is also asked to be thermal efficient and low-cost manufactuable in addition to low NOx emission. Small space for combustor including burner is usually allowed. In this study, parametric study of compact low NOx burner for heating boiler was done using numerical analysis and experiments. Commerical computational fluid dynamic(CFD) program named CFX 5-6 was used for numerical analysis of low NOx burner using turbulent diffusion flame. Comparison of outlet NO and outlet temperature under various equivalence ratio and fuel flow rate was performed between experiment and numerical analysis.

  • PDF

A Current-mode peak detector circuit

  • Riewruja, V.;Linthong, A.;Kaewpoonsuk, A.;Guntapong, R.;Supaph, S.
    • 제어로봇시스템학회:학술대회논문집
    • /
    • 제어로봇시스템학회 2000년도 제15차 학술회의논문집
    • /
    • pp.512-512
    • /
    • 2000
  • In this article, a current mode peak detector circuit is presented. The simple circuit configuration comprises four MOS transistors and one external capacitor. The realization method is suitable fur fabrication using CMOS technology and all transistors are operated in their saturation region. The proposed circuit exhibits a very low drop rate and provides high accuracy, high-speed and wide dynamic range. The proposed circuit has very low power dissipation and operates using a single 2.5V supply. Simulation results confirmed the characteristic of the proposed circuit are also included.

  • PDF

Zr계 벌크 비정질 합금의 변형 모드와 압출 특성의 상관 관계에 관한 연구 (A Study on the Relationship between Deformation Mode and Extrusion Properties for Zr-based Bulk Metallic Glass)

  • 이광석;장영원
    • 한국소성가공학회:학술대회논문집
    • /
    • 한국소성가공학회 2004년도 추계학술대회논문집
    • /
    • pp.199-202
    • /
    • 2004
  • In this present study, an attempt was made to determine the deformation mode of the Zr-Ti-Cu-Ni-Be bulk metallic glass by compression test over a wide range of temperatures and strain rates. From the results, empirical deformation map could be constructed including the boundaries of different deformation modes. Considering power dissipation map and instability map developed on the basis of the Dynamic Materials Model (DMM), the processing map for extrusion could also be constructed. In addition, the macroscopic formability of this BMG alloy has also been examined through the extrusion in laboratory scale within undercooled liquid state. From the results of macroscopic extrusion formability, both deformation map and processing map present good criteria to determine optimal forming conditions.

  • PDF

이동형 시스템에서 프로세서의 전력 소모 최소화를 위한 주파수 선택 알고리즘 (A Frequency Selection Algorithm for Power Consumption Minimization of Processor in Mobile System)

  • 김재진;강진구;허화라;윤충모
    • 디지털산업정보학회논문지
    • /
    • 제4권1호
    • /
    • pp.9-16
    • /
    • 2008
  • This paper presents a frequency selection algorithm for minimization power consumption of processor in Mobile System. The proposed algorithm has processor designed low power processor using clock gating method. Clock gating method has improved the power dissipation by control main clock through the bus which is embedded clock block applying the method of clock gating. Proposed method has compared power consumption considered the dynamic power for processor, selected frequency has considered energy gain and energy consumption for designed processor. Or reduced power consumption with decreased processor speed using slack time. This technique has improved the life time of the mobile systems by clock gating method, considered energy and using slack time. As an results, the proposed algorithm reduce average power saving up to 4% comparing to not apply processor in mobile system.

A 3V-30MHz Analog CMOS Current-Mode Digitally Bandwidth Programmable Integrator

  • Yoon, Kwang-Sub;Hyun, Jai-Sop
    • Journal of Electrical Engineering and information Science
    • /
    • 제2권4호
    • /
    • pp.14-18
    • /
    • 1997
  • A design methodology of the analog current-mode and width programmable integrator for a low voltage (3V) and low power application is developed and the integrator designed by this method is successfully fabricated by the 0.8$\mu\textrm{m}$ CMOS n-well single poly/double metal standard digital process. The integrator occupies the active chip area of 0.3$\textrm{mm}^2$. The experimental result illustrates a low power dissipation (1.0mW∼3.55 mW), 65dB of the dynamic range, and digitally and width programmability (10MHz∼30MHz) with an external digital 4 bit.

  • PDF

미세소자에서 누설전류의 분석과 열화 (Analysis and Degradation of leakage Current in submicron Device)

  • 배지철;이용재
    • 한국전기전자재료학회:학술대회논문집
    • /
    • 한국전기전자재료학회 1996년도 추계학술대회 논문집
    • /
    • pp.113-116
    • /
    • 1996
  • The drain current of the MOSFET in the off state(i.e., Id when Vgs=0V) is undesired but nevertheless important leakage current device parameter in many digital CMOS IC applications (including DRAMs, SRAMs, dynamic logic circuits, and portable systems). The standby power consumed by devices in the off state have added to the total power consumed by the IC, increasing heat dissipation problems in the chip. In this paper, hot-carrier-induced degra- dation and gate-induced-drain-leakage curr- ent under worse case in P-MOSFET\`s have been studied. First of all, the degradation of gate-induced- drain-leakage current due to electron/hole trapping and surface electric field in off state MOSFET\`s which has appeared as an additional constraint in scaling down p-MOSFET\`s. The GIDL current in p-MOSFET\`s was decreased by hot-electron stressing, because the trapped charge were decreased surface-electric-field. But the GIDL current in n-MOS77T\`s under worse case was increased.

  • PDF

A Study on a Repair Technique for a Reinforced Concrete Frame Subjected to Seismic Damage Using Prestressing Cable Bracing

  • Lee, Jin Ho;EI-Ganzory, Hisham
    • Architectural research
    • /
    • 제3권1호
    • /
    • pp.53-60
    • /
    • 2001
  • The proposed building upgrading technique employs prestressing cables to function as bracing to improve the seismic performance during future events. A four-story reinforced concrete moment resisting frame damaged from an ultimate limit state earthquake is assessed and upgraded using the proposed technique. Both existing and upgraded buildings are evaluated in regard of seismic performance parameters performing static lateral load to collapse analysis and dynamic nonlinear time history analysis as well. To obtain realistic comparison of seismic performance between existing and upgraded frames, each frame is subjected to its critical ground motion that has strength demand exceeding the building strength supply. Furthermore, reliability of static lateral load to collapse analysis as a substitute to time history analysis is evaluated. The results reveal that the proposed upgrading technique improves the stiffness distribution compared to the ideal distribution that gives equal inter-story drift. As a result, the upgraded building retains more stories that contribute to energy dissipation. The overall behavior of upgraded building beyond yield is also enhanced due to the gradual change of building stiffness as the lateral load increases.

  • PDF