• 한국정보디스플레이학회:학술대회논문집
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• 2002.08a
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• pp.567-570
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• 2002

The LVDS (Low Voltage Differential Signaling) I/O cells, fully compatible with ANSI TIA/ EIA-644 LVDS standard, are designed using a 0.35${\mu}m$ standard CMOS technology. With a single 3V supply, the core cells operate at 1.34Gbps and power consumption of the output driver and the input receiver is 10. 5mW and 4.2mW, respectively. In the output driver, we employ the DCMFB (Dynamic Common-Mode FeedBack) circuit which can control the DC offset voltage of differential output signals. The SPICE simulation result of the proposed output driver shows that the variation of the DC offset voltage is 15.6% within a permissible range. In the input receiver, the proposed dual input stage with a positive feedback latch covers rail-to-rail input common-mode range and enables a high-speed, low-power operation. 5-channels of the proposed LVDS I/O pair can handle display data up to 8-bit gray scale and UXGA resolution.

• Transactions of the Korean Society for Noise and Vibration Engineering
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• v.13 no.12
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• pp.965-971
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• 2003

To reach high areal density, less track pitch is expected and more servo bandwidth is required. One approach to overcoming the problem is by using dual stage servo system. For this system. we have suggested new milliactuator based on the shear mode of piezoelectric elements to drive the head suspension assembly. In this paper, we introduce milliactuator and controller design method, PQ method. PQ method reduces the controller design problem for DISO (dual-input/single-output) systems to two standard controller design problems for SISO ( single-input/single-output) problems. The first part of PQ method directly addresses the issue of actuator output contribution, and the second part allows the use of traditional loop shaping to achieve the overall system performance. This paper shows how to employ the PQ method to meet aggressive close-loop performance specifications for a disk drive system with a VCM and piezoelectric milliactuator.

• Journal of IKEEE
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• v.23 no.3
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• pp.917-924
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• 2019

This paper presents a wideband low noise amplifier (LNA) that is suitable for LTE-Advanced and 5G communication standards employing carrier aggregation (CA). The proposed LNA encompasses a common input stage and a dual output second stage with a buffer at each distinct output. This architecture is targeted to operate in both intra-band (contiguous and non-contiguous) and inter-band CA. In the proposed design, the input and second stages employ a gm enhancement with resistive feedback technique to achieve self-biasing, enhanced gain, wide bandwidth as well as reduced noise figure of the proposed LNA. An up/down power controller controls the single input single out (SISO) and single input multiple outputs (SIMO) modes of operation for inter-band and intra-band operations. The proposed LNA is designed with a 45nm CMOS technology. For SISO mode of operation, the LNA operates from 0.52GHz to 4.29GHz with a maximum power gain of 17.77dB, 2.88dB minimum noise figure and input (output) matching performance better than -10dB. For SIMO mode of operation, the proposed LNA operates from 0.52GHz to 4.44GHz with a maximum voltage gain of 18.30dB, a minimum noise figure of 2.82dB with equally good matching performance. An $IIP_3$ value of -6.7dBm is achieved in both SISO and SIMO operations. with a maximum current of 42mA consumed (LNA+buffer in SIMO operation) from a 1.2V supply.

• IEIE Transactions on Smart Processing and Computing
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• v.4 no.1
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• pp.44-50
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• 2015

This paper presents a high speed synchronous single inductor dual output boost converter using Type-III compensation for power management in smart devices. Maintaining multiple outputs from a single inductor is becoming very important because of inductor the sizes. The uses of high switching frequency, inductor and capacitor sizes are reduced. Owing to synchronous rectification this kind of converter is suitable for SoC. The phase is controlled in time sharing manner for each output. The controller used here is Type-III, which ensures quick settling time and high stability. The outputs are stable within $58{\mu}s$. The simulation results show that the proposed scheme achieves a better overall performance. The input voltage is 1.8V, switching frequency is 5MHz, and the inductor used is 600nH. The output voltages and powers are 2.6V& 3.3V and 147mW &, 230mW respectively.

• Proceedings of the KIPE Conference
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• 2011.07a
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• pp.145-146
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• 2011

In this paper, a bridgeless flyback power factor correction (PFC) rectifier which uses single magnetic core is proposed. The proposed PFC rectifiers utilize bidirectional switch to handle both positive and negative input voltage without bridge diodes. A transformer with dual output windings enables the rectifier dispense with any additional magnetic component. The operation of the proposed flyback PFC rectifier is analyzed, and its higher efficiency than its conventional counterpart is verified by experiment.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.9C
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• pp.887-895
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• 2009

This paper proposes a cooperative power allocation with the use of partial channel information (e.g., the average signal-to-noise ratio (SNR) and transmit correlation) in multi-cell dual-hop multi-input single-output (MISO) relay systems. In a dual-hop MISO relay channel, it is desirable to allocate the transmit power between dual-hop links to maximize the end-to-end capacity. We consider the maximization of the end-to-end capacity of a dual-hop MISO relay channel under sum-power constraint. The proposed scheme adaptively allocates the transmit power considering the average channel gain of the target relay and the transmit correlation of the desired and inter-relay interference channel from adjacent relays. It is shown by means of upper-bound analysis that the end-to-end capacity can be maximized by making the angle difference of the principal eigenvectors of the desired and inter-relay interference channel orthogonal in highly-correlated channel environments. Finally, the performance of the proposed scheme is verified by computer simulation.

• International Journal of Automotive Technology
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• v.8 no.6
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• pp.771-780
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• 2007

In recent studies, various types of multi mode electric variable transmissions of hybrid electric vehicles have been proposed. Multi mode electric variable transmission consists of two or more different types of planetary gear hybrid powertrain system(PGHP), which can change its power flow type by means of clutches for improving transmission efficiencies. Generally, the power flows can be classified into three different types such as input split, output split and compound split. In this study, we analyzed power transmission characteristics of the possible six input split systems, and found the suitable system for single or multi mode hybrid powertrain. The input split system used in PRIUS is identified as a best system for single mode, and moreover we identified some suitable systems for dual mode.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.6 no.2
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• pp.610-628
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• 2012

Dual carrier frequency offsets (CFOs) occur in multiple-input single-output (MISO)-mode DVB-T2 systems, where signals are transmitted simultaneously from two distributed transmitters in a single frequency network (SFN). In this paper, we first derive an optimal compensation frequency for dual CFOs. We also propose an algorithm that optimizes the compensation frequency for the MISO-mode DVB-T2 application. Its performance is compared with the conventional scheme by using a full DVB-T2 simulator.

• The Transactions of the Korean Institute of Power Electronics
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• v.22 no.2
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• pp.118-125
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• 2017

In this paper, we propose a smart transformer for a smart transformer miniature model, which can replace a 60 [Hz] single-phase transformer installed in an electric vehicle. The proposed smart transformer is lighter than a conventional transformer, can control instantaneous voltage, and can be expected to improve power quality through harmonic compensation. The proposed intelligent transformer consists of an incoming part, an AC/DC converter, and a dual active bridge. Only the incoming part and the AC/DC converter are described in this paper. The proposed intelligent transformer has 75 kVA 3.3 kV input and 750 V DC output, which are verified by simulation and experiment.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2003.11a
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• pp.168-172
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• 2003

This paper analyzes the output noise and the noise figure of common source MOSFET pair each input of which is separately driven in the different frequencies. This analysis is performed for concurrent dual band cascode CMOS LNA with double inputs and single output fabricated in $0.18{\mu}m$ CMOS process. Since both inputs and output are matched to near $50{\Omega}$ using on-chip inductors, the measured noise figures are much higher than those of usual CMOS LNA. But, the main concern of this paper is focused on the added noise features due to the other channel common source stage. The dual-band LNA results in noise figure of 4.54dB at 2.14GHz and 6.03dB at 5.25GHz for selectable operation and 7.44dB and 6.58dB for concurrent operation. The noise analysis explains why the added noise at each band shows so large difference.