• Journal of IKEEE
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• v.23 no.1
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• pp.58-67
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• 2019

A design of an elliptic curve cryptography (ECC) processor that supports both pseudo-random curves and Koblitz curves over $GF(2^m)$ defined by the NIST standard is described in this paper. A finite field arithmetic circuit based on a word-based Montgomery multiplier was designed to support five key lengths using a datapath of fixed size, as well as to achieve a lightweight hardware implementation. In addition, Lopez-Dahab's coordinate system was adopted to remove the finite field division operation. The ECC processor was implemented in the FPGA verification platform and the hardware operation was verified by Elliptic Curve Diffie-Hellman (ECDH) key exchange protocol operation. The ECC processor that was synthesized with a 180-nm CMOS cell library occupied 10,674 gate equivalents (GEs) and a dual-port RAM of 9 kbits, and the maximum clock frequency was estimated at 154 MHz. The scalar multiplication operation over the 223-bit pseudo-random elliptic curve takes 1,112,221 clock cycles and has a throughput of 32.3 kbps.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.24 no.6
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• pp.736-743
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• 2020

Modular multiplication is one of the most important arithmetic operations in public-key cryptography such as elliptic curve cryptography (ECC) and RSA, and the performance of modular multiplier is a key factor influencing the performance of public-key cryptographic hardware. An efficient hardware implementation of word-based Montgomery modular multiplication algorithm is described in this paper. Our modular multiplier was designed to support eleven field sizes for prime field GF(p) and binary field GF(2k) as defined by SEC2 standard for ECC, making it suitable for lightweight hardware implementations of ECC processors. The proposed architecture employs pipeline scheme between the partial product generation and addition operation and the modular reduction operation to reduce the clock cycles required to compute modular multiplication by 50%. The hardware operation of our modular multiplier was demonstrated by FPGA verification. When synthesized with a 65-nm CMOS cell library, it was realized with 33,635 gate equivalents, and the maximum operating clock frequency was estimated at 147 MHz.

• International Journal of Fuzzy Logic and Intelligent Systems
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• v.14 no.2
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• pp.136-144
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• 2014

The existing conventional motion controller does not perform well in the presence of nonlinear properties, uncertain factors, and servo lag phenomena of industrial actuators. Hence, a feasible and effective fuzzy self-tuning proportional integral derivative (PID) and feed-forward control scheme is introduced to overcome these problems. In this design, a fuzzy tuner is used to tune the PID parameters resulting in the rejection of the disturbance, which achieves better performance. Then, both velocity and acceleration feed-forward units are added to considerably reduce the tracking error due to servo lag. To verify the capability and effectiveness of the proposed control scheme, the hardware configuration includes digital signal processing (DSP) which plays the main role, dual-port RAM (DPRAM) to guarantee rapid and reliable communication with the host, field-programmable gate array (FPGA) to handle the task of the address decoder and receive the feed-back encoder signal, and several peripheral logic circuits. The results from the experiments show that the proposed motion controller has a smooth profile, with high tracking precision and real-time performance, which are applicable in various manufacturing fields.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.04b
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• pp.45-48
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• 2002

Poly(3-hexylthiophene) or P3HT based organic thin film transistor (OTFT) array was fabricated on flexible poly carbonate substrates and the electrical characteristics were investigated. As the gate dielectric, a dual layer structure of polyimide-$SiO_2$ was used to improve the roughness of $SiO_2$ surface and further enhancing the device performance and also source-drain electrodes were $O_2$ plasma treated for improvement of the electrical properties, such as drain current and field effect mobility. For the active layer, polymer semiconductor, P3HT layer was printed by contact-printing and spin-coating method. The electrical properties of OTFT devices printed by both methods were evaluated for the comparison. Based on the experiments, P3HT-based OTFT array with field effect mobility of 0.02~0.025 $cm^{2}/V{\cdot}s$ and current modulation (or $I_{on}/I_{off}$ ratio) of $10^{3}\sim10^{4}$ was fabricated.

• Journal of architectural history
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• v.19 no.3
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• pp.71-87
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• 2010

Sewon was a new type of private academy established by a class landed Confucian scholars known as sarim. During Joseon dynasty, sewon had dual functions as a shrine and a place of learning. The site plan of seowon appeared mainly two types of site plan according to the indications of the age and school. This paper was done to analyze the site plan and construction history of Simgok seowon with historical materials and excavation investigation result. Simgok seowon is dedicated to Jo Gwang-jo(1482~1519). This private Confucian academy was founded in 1605 as a small shrine, which was destroyed in 1636. Thereafter, when the shrine received a royal warrant naming as Simgok seowon in 1650, the new site for the seowon was chosen, which is currently located in Gyeonggi-do Yongin-si Sanghyeon-ri 203. Since then, buildings of Simgok seowon was constructed and repaired couple of times. Through the investigation, it was found that the site plan of Simgok seowon was originally a type of 'jeonjaehudang', that is, dormitory building between the lecture hall and the outer gate, or dormitory building is in front and lecture hall is in behind.

• Transactions on Electrical and Electronic Materials
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• v.15 no.3
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• pp.149-154
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• 2014

A new CMOS analog design methodology using an independently optimized self-cascode (SC) is proposed. This idea is based on the concept of the dual-workfunction-gate MOSFETs, which are equivalent to SC structures. The channel length of the source-side MOSFET is optimized, to give higher transconductance ($g_m$) and output resistance ($r_{out}$). The highest $g_m$ and $r_{out}$ of the SC structures are obtained by independently optimizing the channel length ratio of the SC MOSFETs, which is a critical design parameter. An operational amplifier (OPAMP) with the proposed design methodology using a standard digital $0.18-{\mu}m$ CMOS technology was designed and fabricated, to provide better performance. Independently $g_m$ and $r_{out}$ optimized SC MOSFETs were used in the differential input and output stages, respectively. The measured DC gain of the fabricated OPAMP with the proposed design methodology was approximately 18 dB higher, than that of the conventional OPAMP.

• Korean Journal of Fisheries and Aquatic Sciences
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• v.51 no.2
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• pp.178-186
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• 2018

A chirp-echo data acquisition and processing system was developed for use as a simplified, PC-based chirp echo-sounder with some data processing software modules. The design of the software and hardware system was implemented via a field-programmable gate array (FPGA). Digital signal processing algorithms for driving a single-channel chirp transmitter and dual-channel receivers with independent TVG (time varied gain) amplifier modules were incorporated into the FPGA for better real-time performance. The chirp-echo data acquisition and processing system consisted of a notebook PC, an FPGA board, and chirp sonar transmitter and receiver modules, which were constructed using three chirp transducers operating over a frequency range of 35-210 kHz. The functionality of this PC-based chirp echo-sounder was tested in various field experiments. The results of these experiments showed that the developed PC-based chirp echo-sounder could be used in the acquisition, processing and analysis of broadband acoustic echoes related to fish species identification.

• Journal of the Korean Institute of Rural Architecture
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• v.12 no.2
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• pp.135-142
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• 2010

This research aims to examine the characteristics of tomb sites including tomb mound and attached buildings and also to find out the principles reflected in the traditional oriental Feng-Shui location and spatial composition of Junkyung and Youngkyung tomb at Samcheok. The results of this study are as follows. These tombs harmonize with each other in the cosmic dual forces because Junkyung tomb is men's sex symbol and tiger to lie on his belly and Youngkyung tomb is women's sex symbol in geographical feature. Spatial structure in these tomb sites were placed in a reflected line following the hierarchy of metaphysics by standing high Geumchunkyo(Bridge)-Hongsalmun(Gate)-Jegak(Pavilion)-Bongbun(Tomb mound). Axis structure of these tombs is irregular bent-axis type from Geumchunkyo to Bongbun, specially in case of Youngkyung tomb it is getting more refractive. These tombs are divided into and characterized by three zones. Firstly the space for living people constitutes from Geumchunkyo to Hongsalmun, secondly the semi-sacred space constitutes from Hongsalmun to Jegak, and lastly the space for the dead constitutes from the back of Jegak to Bongbun. - type Jegak instead of T type Jegak generally used at Chosun Dynasty was installed because of claypan stretched out in front of Junkyung tomb and Bongbun of Youngkyung tomb located at a ravine between two mountain ranges.

• Proceedings of the KIEE Conference
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• 2006.10a
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• pp.65-66
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• 2006

AIGaN/GaN 고전자 이동도 트랜지스터 (High Electron Mobility Transistors, HEMTs)는 와이드 밴드-갭과 높은 항복 전계 및 우수한 채널 특성으로 인해 마이크로파 응용분야와 전력용 반도체에서 각광받고 있다. 최근, 전력 응용분야에서 요구되는 높은 항복 전압과 출력, 우수한 주파수 특성을 획득하기 인해 이중 게이트 AIGaN/GaN HEHTs에 관한 연구가 발표되고 있다. 본 논문에서는 AIGaN/GaN HEMTs에 이중 게이트를 적용하여, 두 개의 게이트와 드레인, 소스의 누설 전류를 각각 측정하여 이중 게이트 AIGaN/GaN HEMTS의 누설 전류 메커니즘을 분석하였다. 또한 제안된 소자의 $SiO_2$ 패시베이션 전 후의 누설 전류 특성을 비교하였다. $SiO_2 $ 패시베이션되지 않은 소자의 누설 전류는 드레인, 소스와 추가 게이트로부터 주 게이트로 흐른 반면, 패시베이션 된 소자 누설 전류는 드레인으로부터 주 게이트 방향의 누설 전류만 존재하였다. $SiO_2$ 패시베이션 된 소자의 누설 전류는 (87.31 nA ) 패시베이션 되지 않은 소자의 누설 전류 ( $8.54{\mu}A$ )에 비해 의게 감소하였다.

• ETRI Journal
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• v.42 no.5
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• pp.773-780
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• 2020

A 40 nm complementary metal oxide semiconductor carrier-aggregated drive amplifier with high linearity is presented for sub-GHz Internet of Things applications. The proposed drive amplifier consists of two high linear amplifiers, which are composed of five differential cascode cells. Carrier aggregation can be achieved by switching on both the driver amplifiers simultaneously and combining the two independent signals in the current mode. The common gate bias of the cascode cells is selected to maximize the output 1 dB compression point (P1dB) to support high-linear wideband applications, and is used for the local supply voltage of digital circuitry for gain control. The proposed circuit achieved an output P1dB of 10.7 dBm with over 22.8 dBm of output 3rd-order intercept point up to 0.9 GHz and demonstrated a 55 dBc adjacent channel leakage ratio (ACLR) for the 802.11af with -5 dBm channel power. To the best of our knowledge, this is the first demonstration of the wideband carrier-aggregated drive amplifier that achieves the highest ACLR performance.