• Journal of Power Electronics
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• 제14권5호
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• pp.815-826
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• 2014

An improved bridgeless interleaved boost power factor correction (PFC) rectifier to improve power efficiency and component utilization is proposed in this study. With combined conventional bridgeless PFC circuit and interleaved technology, the proposed rectifier consists of two interleaved and magnetic inter-coupling boost bridgeless converter cells. Each cell operates alternatively in the critical conduction mode, which can achieve the soft-switching characteristics of the switches and increase power capacity. Auxiliary blocking diodes are employed to eliminate undesired circulating loops and reduce current-sensing noise, which are among the serious drawbacks of a dual-boost PFC rectifier. Magnetic component utilization is improved by symmetrically coupling two inductors on a unique core, which can achieve independence from each other based on the auxiliary diodes. Through the interleaved approach, each switch can operate in the whole line cycle. A simple control scheme is employed in the circuit by using a conventional interleaved controller. The operation principle and theoretical analysis of the converter are presented. A 600 W experimental prototype is built to verify the theoretical analysis and feasibility of the proposed rectifier. System efficiency reaches 97.3% with low total harmonic distortion at full load.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2012년도 전력전자학술대회 논문집
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• pp.399-400
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• 2012

The proposed battery charger presented in this paper is suitable for Lead-Acid Battery and the dc/dc buck converter topology is applied as a charger circuit. The technique adopted in this charger is constant current & constant voltage dual mode, which is decided by the value of voltage of proposed battery. Automatic mode change function is detected by the percentage value of level of battery charging. CC Mode (Constant Current Mode) is operated when charging level is below 80% of the total charging of Battery voltage and above 80% of battery voltage charging, CV Mode (Constant Voltage Mode) is automatically operated. As the charging level exceeds 120%, it automatically terminates charging. The feedback signal to the PWM generator for charging the battery is controlled by using the current and voltage measurement circuits simultaneously. This technique will degrade the damage of proposed type of battery and improve the power efficiency of charger. Finally, a prototype charger circuit designed for a 12-V 7-Ah lead acid battery is constructed and tested to confirm the theoretical predictions. Satisfactory performance is obtained from simulation and the experimental results.

• Journal of Power Electronics
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• 제19권1호
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• pp.119-133
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• 2019

Although the dual modulation wave method can solve the low-frequency neutral point potential (NPP) fluctuation problem for three-level neutral point clamped converters, it also increases the switching frequency and limits the zero-sequence voltage. That makes it harmful when dealing with the NPP drift problem if the converter suffers from a long dead time or asymmetric loads. By introducing two degrees of freedom (2-DOF), an NPP control based on a search optimization method can demonstrate its ability to cope with the above mentioned two types of NPP problems. However, the amount of calculations for obtaining an optimal 2-DOF is so large that the method cannot be applied to certain industrial applications with an inexpensive digital signal processor. In this paper, a novel optimal 2-DOF-based NPP control is proposed. The relationships between the NPP and the 2-DOF are analyzed and a method for directly determining the optimal 2-DOF is also discussed. Using a direct calculation method, the amount of calculations is significantly reduced. In addition, the proposed method is able to maintain the strongest control ability for the two types of NPP problems. Finally, some experimental results are given to confirm the validity and feasibility of the proposed method.

• ETRI Journal
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• 제30권3호
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• pp.347-354
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• 2008

In this paper, the design of a low-power 512-bit synchronous EEPROM for a passive UHF RFID tag chip is presented. We apply low-power schemes, such as dual power supply voltage (VDD=1.5 V and VDDP=2.5 V), clocked inverter sensing, voltage-up converter, I/O interface, and Dickson charge pump using Schottky diode. An EEPROM is fabricated with the 0.25 ${\mu}m$ EEPROM process. Power dissipation is 32.78 ${\mu}W$ in the read cycle and 78.05 ${\mu}W$ in the write cycle. The layout size is 449.3 ${\mu}m$ ${\times}$ 480.67 ${\mu}m$.

• 한국생산제조학회지
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• 제19권6호
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• pp.724-730
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• 2010

A load cell is a converter that generates voltage signals when a certain force is effected in a given direction. An essential measurement device for electronic scales that indicate weight by numbers. These load cells are being applied in various areas such as daily life, distribution, laboratory and industrial. Recently the study to manufacture load cells in a more simple method while increasing performance is being persisted. In this study based on the comparison of load cells manufactured through single surface processing using strain gauges. Those manufactured through dual surface processing using strain gauges. Ultimately persist a more simple method of load cell manufacturing while increasing its performance. The elements that were compared were linearity, hysteresis, creep and eccentricity which are short tenn performance factors. The conclusion was that single surface processing showed almost identical data as that of dual surface processing, and the load cell error rate(0.005%) also excess regulation. The manufacturing time was shortened while mass-production was possible. Which indicates a development in the weighing industry.

• Journal of information and communication convergence engineering
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• 제13권4호
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• pp.235-240
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• 2015

A decimation chain for multi-standard reconfigurable radios is presented for 900-MHz and 1,900-MHz dual-band cellular standards with a data interpolator based on the Lagrange method for adjusting the variable data rate to a fixed data rate appropriate for each standard. The two proposed configurations are analyzed and compared to provide insight into aliasing and the signal bandwidth by means of a newly introduced measure called interpolation error. The average interpolation error is reduced as the ratio of the sampling frequency to the signal BW is increased. The decimation chain and the multi-rate analog-to-digital converter are simulated to compute the interpolation error and the output signal-to-noise ratio. Further, a method to operate the above-mentioned chain under a compressed mode of operation is proposed in order to guarantee continuous packet connectivity for inter-radio-access technologies. The presented decimation chain can be applied to LTE, WCDMA, GSM multi-mode multi-band digital front-end which will ultimately lead to the software-defined radio.

• Journal of Power Electronics
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• 제16권2호
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• pp.553-563
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• 2016

This paper presents a digital hardware implementation of a real-time simulator for a multiphase drive using a field-programmable gate array (FPGA) device. The simulator was developed with a modular and hierarchical design using very high-speed integrated circuit hardware description language (VHDL). Hence, this simulator is flexible and portable. A state-space representation model suitable for FPGA implementations was proposed for a dual three-phase induction machine (DTPIM). The simulator also models a two-level 12-pulse insulated-gate bipolar transistor (IGBT)-based voltage-source converter (VSC), a pulse-width modulation scheme, and a measurement system. Real-time simulation outputs (stator currents and rotor speed) were validated under steady-state and transient conditions using as reference an experimental test bench based on a DTPIM with 15 kW-rated power. The accuracy of the proposed digital hardware implementation was evaluated according to the simulation and experimental results. Finally, statistical performance parameters were provided to analyze the efficiency of the proposed DTPIM hardware implementation method.

• Journal of Power Electronics
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• 제11권4호
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• pp.456-463
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• 2011

Grid-connected converters have widely adopted LCL filters to acquire high harmonic suppression. However, the LCL filter increases the system order so that the design of the system stability would be complicated. Recently, sole-loop control strategies have been used for grid-connected converters with L or LC filters. But if the sole-loop control is directly transplanted to grid-connected converters with LCL filters, the systems may be unstable. This paper presents a novel dual-loop power control strategy composed of a power outer loop and a current inner loop. The outer loop regulates the grid-connected power. The inner loop improves the system stability margin and suppresses the resonant peak caused by the LCL filter. To obtain the control variables, a single-phase current detection is proposed based on PQ theory. The system transfer function is derived in detail and the influence of control gains on the system stability is analyzed with the root locus. Simulation and experimental results demonstrate the feasibility of the proposed control.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2007년도 하계학술대회 논문집
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• pp.132-134
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• 2007

하이브리드 차량 및 전기차량 구동 모터의 권선저항에 의한 손실 및 모터의 크기를 줄이기 위해 고효율, 고승압형 DC-DC 컨버터 사용이 요구된다. 기존의 부스트 컨버터는 기생저항 성분에 의해 고승압이 불가능하여 변압기를 사용하여 승압비를 향상시킨 current-fed push-pull, current-fed full bridge, dual inductor-fed 부스트 컨버터 등으로 변형되어 사용되어 왔다. dual inductor-fed 부스트 컨버터의 경우 동일조건하에서 앞서 기술된 2가지 컨버터보다 2배의 승압비를 얻을 수 있으며 1차측 전류 스트레스가 낮은 장점을 가지고 있어 대전력, 고승압 응용에 적합하다. 하지만 변압기의 누설인덕턴스에 의한 써지성 전류/전압을 제한하기 위한 부가적인 snubber회로의 사용으로 효율을 떨어뜨리게 되는 단점을 가지고 있다. 본 논문에서는 이러한 단점을 보완할 수 있는 새로운 2개의 인덕터와 1개의 변압기를 갖는 DC-DC 컨버터를 제안한다. 제안된 컨버터의 동작원리와 모드해석을 실시하고 최종적으로 400W, 42Vdc (Battery)/400Vdc (Electric Motor) 실험결과를 통해 이를 검증한다.

• 전력전자학회논문지
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• 제27권6호
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• pp.507-514
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• 2022

This study proposes an optimal design process for a high-frequency transformer that has a large leakage inductance for dual-active-bridge converters. Notably, conventional design processes have large errors in designing leakage transformers because mathematically modeling the leakage inductance of such transformers is difficult. In this work, the geometric parameters of a shell-type transformer are identified, and finite element analysis(FEA) simulation is performed to determine the magnetization inductance, leakage inductance, and copper loss of various shapes of shell-type transformers. Regression models for magnetization and leakage inductances and copper loss are established using the simulation results and the machine learning technique. In addition, to improve the regression models' performance, the regression models are tuned by adding featured parameters that consider the physical characteristics of the transformer. With the regression models, optimal high-frequency transformer designs and the Pareto front (in terms of volume and loss) are determined using NSGA-II. In the Pareto front, a desirable optimal design is selected and verified by FEA simulation and experimentation. The simulated and measured leakage inductances of the selected design match well, and this result shows the validity of the proposed design process.