• Journal of Korea Society of Industrial Information Systems
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• v.20 no.6
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• pp.29-36
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• 2015

This paper presents an LED backlight driver IC consisting of three linear current regulators and an output-voltage regulation loop with a self-adjustable reference voltage. In the proposed LED driver, the output voltage is controlled by dual feedback loops. The first loop senses and controls the output voltage, and the second loop senses the voltage drop of the linear current regulator and adjusts the reference voltage. With these feedback loops, the voltage drop of the linear current regulator is maintained at a minimum value, at which the driver efficiency is maximized. The output of the driver is a three-channel LED setup with four LEDs in each channel. The luminance is adjusted by the PWM dimming signal. The proposed driver is designed by a $0.35-{\mu}m$ 60-V high-voltage process, resulting in an experimental maximum efficiency of approximately 85%.

• Journal of IKEEE
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• v.23 no.3
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• pp.994-1002
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• 2019

In this paper, we propose the development of a power conversion system for electric power take-off (e-PTO) of agricultural electric vehicles. Most e-PTOs use commercial power $220V_{AC}$. A bidirectional power conversion system having a two-stage structure consisting of a DC-DC converter and a DC-AC inverter for supplying a high output voltage using a low battery voltage of an agricultural electric vehicle is suitable. we propose a power conversion system consisting of the one-stage dual active bridge (DAB) converter and the two-stage bidirectional full bridge inverter. In addition, we propose a soft start algorithm for reducing the inrush current generated by the link capacitor charging during the initial operation. A 3kW prototype system and its corresponding algorithms have been implemented to verify its effectiveness through experiments.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.8
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• pp.35-40
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• 2012

In DC-DC converters, a PWM/PFM dual mode control method is commonly used to maintain a high efficiency over a wide range of load variation. Since the control mode is selected according to the load condition, the chip area is increased due to additional circuit for mode control and the optimum efficiency cannot be achieved around the mode transition point. To solve such problems, a new integrated control method is proposed in this paper, in which a PLL is used in the current mode PWM control circuit instead of an oscillator. The proposed integrated control method is verified through a design of a buck converter using PSIM simulation. Simulation of the complete buck converter circuit by Cadence Spectre showed a maximum efficiency of 94.7% at a load current of 250mA and an efficiency of 85.4% at a load current of 10mA under the light load condition.

• Journal of Sensor Science and Technology
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• v.27 no.2
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• pp.93-98
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• 2018

In this paper, an energy-efficient 11.49-bit successive approximation register (SAR) capacitance-to-digital converter (CDC) for capacitive sensors with a figure of merit (FoM) of 31.6 pJ/conversion-step is presented. The CDC employs a SAR algorithm to obtain low power consumption and a simplified structure. The proposed circuit uses a capacitive sensing amplifier (CSA) and a dynamic latch comparator to achieve parasitic capacitance-insensitive operation. The CSA adopts a correlated double sampling (CDS) technique to reduce flicker (1/f) noise to achieve low-noise characteristics. The SAR algorithm is implemented in dual operating mode, using an 8-bit coarse programmable capacitor array in the capacitance-domain and an 8-bit R-2R digital-to-analog converter (DAC) in the charge-domain. The proposed CDC achieves a wide input capacitance range of 29.4 pF and a high resolution of 0.449 fF. The CDC is fabricated in a $0.18-{\mu}m$ 1P6M complementary metal-oxide-semiconductor (CMOS) process with an active area of 0.55 mm2. The total power consumption of the CDC is $86.4{\mu}W$ with a 1.8-V supply. The SAR CDC achieves a measured 11.49-bit resolution within a conversion time of 1.025 ms and an energy-efficiency FoM of 31.6 pJ/step.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.3
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• pp.33-42
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• 2003

This paper describes an efficient design of an asynchronous 16-bit divider using the NST (new Svoboda-Tung) algorithm. The divider is designed to reduce power consumption by using the asynchronous design scheme in which the division operation is performed only when it is requested. The divider consists of three blocks, i.e. pre-scale block, iteration step block, and on-the-fly converter block using asynchronous pipeline structure. The pre-scale block is designed using a new subtracter to have small area and high performance. The iteration step block consists of an asynchronous ring structure with 4 division steps for area reduction. In other to reduce hardware overhead, the part related to critical path is designed by a dual-rail circuit, and the other part is done by a single-rail circuit in the ring structure. The on-the-fly converter block is designed for high performance using the on-the-fly algorithm that enables parallel operation with iteration step block. The design results with 0.6${\mu}{\textrm}{m}$ CMOS process show that the divider consists of 12,956 transistors with 1,480 $\times$1,200${\mu}{\textrm}{m}$$^2$area and average-case delay is 41.7㎱.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.22 no.5
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• pp.31-40
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• 2008

Recently, Contactless Power Supply(CPS) system has been broadly studied as a power supply system for Flat Panel Display(FPD) material transfer equipments. In mass production line, CPS systems on material transfer equipment are applied only in the straight sections with single operating vehicle. The formal CPS system was not adequate for curved section nor multiple operating vehicles. Therefore, this paper presents CPS system that consists of straight and curved section with multiple operation vehicles. The circuit topology of CPS system consists of full bridge configured serial-parallel resonant DC/DC converter. The control method for CPS system consists of duty control method on the primary power supply system to maintain constant resonant current. And the secondary power supply systems of multiple vehicles are self controled to maintain constant output voltage. Practically, the test result of dual vehicles on straight and curved section of material transfer equipments were satisfactory, and proved it's applicability on commercial use.

• Journal of IKEEE
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• v.23 no.3
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• pp.1104-1107
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• 2019

This paper proposes a DC-DC boost converter for wearable AMOLED display using dead time controller to reduce dead time and improve power efficiency. Also the DC-DC boost converter adopts PWM-SPWM (set-time variable pulse width modulation) dual-mode to enhance power efficiency under light load and decrease output voltage ripple. The proposed circuit has been designed using $0.18{\mu}m$ BCDMOS process. Simulation results show that the circuit has power efficiency of 39%~96% and output ripple voltage of 2 mV under load current range of 1 mA~70 mA. The power efficiency of the proposed circuit is up to 2% higher than the previous PWM-SPWM method and up to 8% higher than only PWM method.

• ETRI Journal
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• v.38 no.4
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• pp.665-674
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• 2016

We designed and fabricated a semiconductor optical amplifier-integrated dual-mode laser (SOA-DML) as a compact and widely tunable continuous-wave terahertz (CW THz) beat source, and a pin-photodiode (pin-PD) integrated with a log-periodic planar antenna as a CW THz emitter. The SOA-DML chip consists of two distributed feedback lasers, a phase section for a tunable beat source, an amplifier, and a tapered spot-size converter for high output power and fiber-coupling efficiency. The SOA-DML module exhibits an output power of more than 15 dBm and clear four-wave mixing throughout the entire tuning range. Using integrated micro-heaters, we were able to tune the optical beat frequency from 380 GHz to 1,120 GHz. In addition, the effect of benzocyclobutene polymer in the antenna design of a pin-PD was considered. Furthermore, a dual active photodiode (PD) for high output power was designed, resulting in a 1.7-fold increase in efficiency compared with a single active PD at 220 GHz. Finally, herein we successfully show the feasibility of the CW THz system by demonstrating THz frequency-domain spectroscopy of an ${\alpha}$-lactose pellet using the modularized SOA-DML and a PD emitter.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.6
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• pp.760-770
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• 2016

A 12-bit 750 kS/s Dual-Sampling Successive Approximation Register Analog-to-Digital Converter (SAR ADC) technique with reduced Capacitive DAC (CDAC) is presented in this paper. By adopting the Adaptive Power Control (APC) technique for the two-stage latched type comparator and using bootstrap switch, power consumption can be reduced and overall system efficiency can be optimized. Bootstrapped switches also are used to enhance the sampling linearity at a high input frequency. The proposed SAR ADC reduces the average switching energy compared with conventional SAR ADC by adopting reduced the Most Significant Bit (MSB) cycling step with Dual-Sampling of the analog signal. This technique holds the signal at both comparator input asymmetrically in sample mode. Therefore, the MSB can be calculated without consuming any switching energy. The prototype SAR ADC was implemented in $0.18-{\mu}m$ CMOS technology and occupies $0.728mm^2$. The measurement results show the proposed ADC achieves an Effective Number-of-Bits (ENOB) of 10.73 at a sampling frequency of 750 kS/s and clock frequency of 25 MHz. It consumes only 0.13 mW from a 5.0-V supply and achieves the INL and DNL of +2.78/-2.45 LSB and +0.36/-0.73 LSB respectively, SINAD of 66.35 dB, and a Figures-of-Merit (FoM) of a 102 fJ/conversion-step.

• Journal of Power Electronics
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• v.15 no.6
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• pp.1456-1467
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• 2015

This paper presents a novel close-loop control scheme based on small signal modeling and weighted composite voltage feedback for a three-phase input and single-phase output Matrix Converter (3-1MC). A small non-polar capacitor is employed as the decoupling unit. The composite voltage weighted by the load voltage and the decoupling unit voltage is used as the feedback value for the voltage controller. Together with the current loop, the dual-loop control is implemented in the 3-1MC. In this paper, the weighted composite voltage expression is derived based on the sinusoidal pulse-width modulation (SPWM) strategy. The switch functions of the 3-1MC are deduced, and the average signal model and small signal model are built. Furthermore, the stability and dynamic performance of the 3-1MC are studied, and simulation and experiment studies are executed. The results show that the control method is effective and feasible. They also show that the design is reasonable and that the operating performance of the 3-1MC is good.