• 제목/요약/키워드: Dual Scaling

검색결과 27건 처리시간 0.024초

Fuzzy Inference in Medical Diagnosis

  • Kim, Soon-Ki
    • 한국지능시스템학회:학술대회논문집
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    • 한국퍼지및지능시스템학회 1995년도 추계학술대회 학술발표 논문집
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    • pp.92-97
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    • 1995
  • In medical diagnostic process we are dealing with the preliminary diagnosis based on the interview chart. We will quantify the qualitative information of a patient by dual scaling and establish both prototypes of fuzzy diagnostic sets and the fuzzy linear regressions. Its utility is shown in the diagnosis of headache and CAFDDH.

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Optimization-based Image Watermarking Algorithm Using a Maximum-Likelihood Decoding Scheme in the Complex Wavelet Domain

  • Liu, Jinhua;Rao, Yunbo
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • 제13권1호
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    • pp.452-472
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    • 2019
  • Most existing wavelet-based multiplicative watermarking methods are affected by geometric attacks to a certain extent. A serious limitation of wavelet-based multiplicative watermarking is its sensitivity to rotation, scaling, and translation. In this study, we propose an image watermarking method by using dual-tree complex wavelet transform with a multi-objective optimization approach. We embed the watermark information into an image region with a high entropy value via a multiplicative strategy. The major contribution of this work is that the trade-off between imperceptibility and robustness is simply solved by using the multi-objective optimization approach, which applies the watermark error probability and an image quality metric to establish a multi-objective optimization function. In this manner, the optimal embedding factor obtained by solving the multi-objective function effectively controls watermark strength. For watermark decoding, we adopt a maximum likelihood decision criterion. Finally, we evaluate the performance of the proposed method by conducting simulations on benchmark test images. Experiment results demonstrate the imperceptibility of the proposed method and its robustness against various attacks, including additive white Gaussian noise, JPEG compression, scaling, rotation, and combined attacks.

비대칭 축소 및 확대가 가능한 조합 보간 알고리즘의 실시간 처리를 위한 하드웨어 설계 (Hardware Design for Real-Time Processing of a Combinatorial Interpolation Scaler with Asymmetric Down-scaling and Up-scaling)

  • 한시연;정세민;손정현;이재성;강봉순
    • 전기전자학회논문지
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    • 제28권1호
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    • pp.26-32
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    • 2024
  • 최근 다양한 영상의 해상도 포맷이 등장하였고, 디지털 기기는 이를 지원하기 위해 입력 영상의 해상도를 확대 또는 축소하는 전용 스케일러 칩을 내장하고 있다. 따라서 스케일러 칩의 성능과 하드웨어 크기는 중요하다고 할 수 있다. 본 논문에서는 Han이 제안한 조합 보간 스케일러 알고리즘을 Han, Jung이 제안한 Dual-clock을 가지는 라인 메모리 구조를 이용해 하드웨어 설계를 진행하였다. 제안하는 하드웨어는 QHD 환경에서 실시간으로 처리가 가능한 구조로, Verilog를 이용해 설계되었으며 Xilinx Vivado 2023.1을 이용하여 검증하였다. 또한 Han이 제안한 알고리즘과 하드웨어의 정량적 수치 평가 비교를 통해 성능을 검증하였다.

Self-Tuning Fuzzy Logic Controller for a Dual Star Induction Machine

  • Merabet, Elkheir;Amimeur, Hocine;Hamoudi, Farid;Abdessemed, Rachid
    • Journal of Electrical Engineering and Technology
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    • 제6권1호
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    • pp.133-138
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    • 2011
  • This paper proposes a simple but robust self-tuning fuzzy logic controller for the speed regulation of a dual star induction machine based on indirect field oriented control. For feed the two star of this machine, two voltage source inverters based on sinus-triangular pulse-width modulation techniques are introduced. The simulation results show the robustness and good performance of the proposed controller.

Development of a Dual-Circular Polarizer for the KVN Receivers

  • Chung, Moon-Hee;Je, Do-Heung;Han, Seog-Tae;Lee, Jung-Won
    • Journal of Astronomy and Space Sciences
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    • 제26권3호
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    • pp.345-354
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    • 2009
  • A stepped septum polarizer has been designed and fabricated for the 43 GHz band KVN receiver system. The dual-circular polarizer converts left and right hand circularly polarized signals into linear polarizations in two separated rectangular waveguides. Measurements show that the performance of the designed septum polarizer covering 42-48 GHz frequency band is adequate to meet the requirement of KVN receivers. Especially, a polarizer for the KVN receiver of 85-95 GHz frequency band can be fabricated by scaling the dimensions of the septum polarizer developed in this paper.

A Low-Power Register File with Dual-Vt Dynamic Bit-Lines driven by CMOS Bootstrapped Circuit

  • Lee, Hyoung-Wook;Lee, Hyun-Joong;Woo, Jong-Kwan;Shin, Woo-Yeol;Kim, Su-Hwan
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제9권3호
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    • pp.148-152
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    • 2009
  • Recent CMOS technology scaling has seriously eroded the bit-line noise immunity of register files due to the consequent increase in active bit-line leakage currents. To restore its noise immunity while maintaining performance, we propose and evaluate a $256{\times}40$-bit register file incorporating dual-$V_t$ bit-lines with a boosted gate overdrive voltage in 65 nm bulk CMOS technology. Simulation results show that the proposed bootsrapping scheme lowers leakage current by a factor of 450 without its performance penalty.

선형계획을 위한 쌍대신경망 (Primal-Dual Neural Network for Linear Programming)

  • 최혁준;장수영
    • 한국경영과학회지
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    • 제17권1호
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    • pp.3-16
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    • 1992
  • We present a modified Tank and Hopfield's neural network model for solving Linear Programming problems. We have found the fact that the Tank and Hopfield's neural circuit for solving Linear Programming problems has some difficulties in guaranteeing convergence, and obtaining both the primal and dual optimum solutions from the output of the circuit. We have identified the exact conditions in which the circuit stops at an interior point of the feasible region, and therefore fails to converge. Also, proper scaling of the problem parameters is required, in order to obtain a feasible solution from the circuit. Even after one was successful in getting a primal optimum solution, the output of the circuit must be processed further to obtain a dual optimum solution. The modified model being proposed in the paper is designed to overcome such difficulties. We describe the modified model and summarize our computational experiment.

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Design of 32 bit Parallel Processor Core for High Energy Efficiency using Instruction-Levels Dynamic Voltage Scaling Technique

  • Yang, Yil-Suk;Roh, Tae-Moon;Yeo, Soon-Il;Kwon, Woo-H.;Kim, Jong-Dae
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제9권1호
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    • pp.1-7
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    • 2009
  • This paper describes design of high energy efficiency 32 bit parallel processor core using instruction-levels data gating and dynamic voltage scaling (DVS) techniques. We present instruction-levels data gating technique. We can control activation and switching activity of the function units in the proposed data technique. We present instruction-levels DVS technique without using DC-DC converter and voltage scheduler controlled by the operation system. We can control powers of the function units in the proposed DVS technique. The proposed instruction-levels DVS technique has the simple architecture than complicated DVS which is DC-DC converter and voltage scheduler controlled by the operation system and a hardware implementation is very easy. But, the energy efficiency of the proposed instruction-levels DVS technique having dual-power supply is similar to the complicated DVS which is DC-DC converter and voltage scheduler controlled by the operation system. We simulate the circuit simulation for running test program using Spectra. We selected reduced power supply to 0.667 times of the supplied power supply. The energy efficiency of the proposed 32 bit parallel processor core using instruction-levels data gating and DVS techniques can improve about 88.4% than that of the 32 bit parallel processor core without using those. The designed high energy efficiency 32 bit parallel processor core can utilize as the coprocessor processing massive data at high speed.

A Coupled Higher-Order Nonlinear $Schr{\ddot{o}}dinger$ Equation Including Higher-Order Bright and Dark Solitons

  • Kim, Jong-Bae
    • ETRI Journal
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    • 제23권1호
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    • pp.9-15
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    • 2001
  • We suggest a generalized Lax pair on a Hermitian symmetric space to generate a new coupled higher-order nonlinear $Schr{\ddot{o}}dinger$ equation of a dual type which contains both bright and dark soliton equations depending on parameters in the Lax pair. Through the generalized ways of reduction and the scaling transformation for the coupled higher-order nonlinear $Schr{\ddot{o}}dinger$ equation, two integrable types of higher-order dark soliton equations and their extensions to vector equations are newly derived in addition to the corresponding equations of the known higher-order bright solitons. Analytical discussion on a general scalar solution of the higher-order dark soliton equation is then made in detail.

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IFS DECISION MAKING PROCESSES TO DIFFERENTIAL DIAGNOSIS OF HEADACHE

  • Kim, Soon-Ki
    • 한국지능시스템학회:학술대회논문집
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    • 한국퍼지및지능시스템학회 1998년도 The Third Asian Fuzzy Systems Symposium
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    • pp.264-267
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    • 1998
  • We are dealing with the preliminary diagnosis from the information of headache interview chart. We quantify the qualitative information based on the interview chart by dual scaling. Prototype of fuzzy diagnostic sets and the neural linear regression methods are established with these quantified data, These new methods can be used to classify new patient's tone of diseases with certain degrees of belief and its concerned symptoms. We call these procedures as neural Fuzzy Differential Diagnosis of Headache (NFDDH-1). Also we investigate three measures to medical diagnosis, where relations between symptoms and diseases are described by intutionistic fuzzy set (IFS) data. Two measures are described by nin-max and max-min IFS operators, respectively. Another measure is the similarity degree, i.e., IFS distance between patient's symptoms and prototypes of diseases. We consider some reasonable criteria for three measures in order to determine the label of headache, We will establish hree measures in NFDDH-2 and combine two packages as NFDDH

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