• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.10
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• pp.2209-2216
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• 2011

In this paper, we design a 32-bit eFuse OTP memory for PMICs using MagnaChip's $0.18{\mu}m$ process. We solve a problem of an electrical shortage between an eFuse link and the VSS of a p-substrate in programming by placing an n-well under the eFuse link. Also, we propose a WL driver circuit which activates the RWL (read word-line) or WWL (write word-line) of a dual-port eFuse OTP memory cell selectively when a decoded WERP (WL enable for read or program) signal is inputted to the eFuse OTP memory directly. Furthermore, we reduce the layout area of the control circuit by removing a delay chain in the BL precharging circuit. We'can obtain an yield of 100% at a program voltage of 5.5V on 94 manufactured sample dies when measured with memory tester equipment.

• JSTS:Journal of Semiconductor Technology and Science
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• v.9 no.1
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• pp.1-7
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• 2009

This paper describes design of high energy efficiency 32 bit parallel processor core using instruction-levels data gating and dynamic voltage scaling (DVS) techniques. We present instruction-levels data gating technique. We can control activation and switching activity of the function units in the proposed data technique. We present instruction-levels DVS technique without using DC-DC converter and voltage scheduler controlled by the operation system. We can control powers of the function units in the proposed DVS technique. The proposed instruction-levels DVS technique has the simple architecture than complicated DVS which is DC-DC converter and voltage scheduler controlled by the operation system and a hardware implementation is very easy. But, the energy efficiency of the proposed instruction-levels DVS technique having dual-power supply is similar to the complicated DVS which is DC-DC converter and voltage scheduler controlled by the operation system. We simulate the circuit simulation for running test program using Spectra. We selected reduced power supply to 0.667 times of the supplied power supply. The energy efficiency of the proposed 32 bit parallel processor core using instruction-levels data gating and DVS techniques can improve about 88.4% than that of the 32 bit parallel processor core without using those. The designed high energy efficiency 32 bit parallel processor core can utilize as the coprocessor processing massive data at high speed.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.10
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• pp.138-142
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• 2016

Dual-energy digital radiography (DEDR) has been used for detecting lesions within the body using energy subtraction methods. The purpose of this study was to acquire optimal bone and tissue image by changing physical factors such as Tube voltage (kVp) and add filters, and then we compared with the predicted values using SRS-78 program and experimental results. For that purpose, we acquired images according to changes in physical parameters of various materials since we had to acquire the optimal bone and tissue image using energy subtraction. Used phantom consists of aluminum and polymethyl methacrylate (PMMA) and a comparison of image optimization was measured by contrast-to-noise ratio (CNR). In results, first of all, we confirmed that a subtraction image from 50 kVp image and 120 kVp image is optimal bone and tissue image. Also when we added a 10 mm Aluminum add filter, we expected it is a result of the optimal bone and tissue image. Besides, we confirmed these results are consistent with the predicted optimized condition by SRS-78 program.. In conclusion, we indicated that we can acquire optimal bone and tissue image by controling physical factors such as kVp, add filters through this study. Also we expected that DEDR will contribute to the field of medical imaging technology.

• Proceedings of the KIEE Conference
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• 1996.07b
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• pp.1313-1315
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• 1996

This paper presents a new method to obtain more stable and precise A/D conversion for remote sensing use. Hardware is designed to compensate offset voltage and drift & temperature characteristics, as well as to perform dual slop A/D converter by using single chip microprocessor. Serial communication program which is based on ASCII code commands is also developed to add initial setup & calibration functions as well as to perform A/D data communication. Proposed method will give a good applications to the industrial field where a high precision remote sensing is required.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.17 no.9
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• pp.21-26
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• 2016

This paper presents a step-down DC-DC buck converter with a CCM/DCM dual-mode function for the internal power stage of portable electronic device. The proposed converter that is operated with a high frequency of 1 MHz consists of a power stage and a control block. The power stage has a power MOS transistor, inductor, capacitor, and feedback resistors for the control loop. The control part has a pulse width modulation (PWM) block, error amplifier, ramp generator, and oscillator. In this paper, an external capacitor for compensation has been replaced with a multiplier equivalent CMOS circuit for area reduction of integrated circuits. In addition, the circuit includes protection block, such as over voltage protection (OVP), under voltage lock out (UVLO), and thermal shutdown (TSD) block. The proposed circuit was designed and verified using a $0.18{\mu}m$ CMOS process parameter by Cadence Spectra circuit design program. The SPICE simulation results showed a peak efficiency of 94.8 %, a ripple voltage of 3.29 mV ripple, and a 1.8 V output voltage with supply voltages ranging from 2.7 to 3.3 V.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.10 no.5
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• pp.455-461
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• 2017

In this paper, a local DL (Data Line) sensing method with smaller parasitic capacitance replacing the previous distributed DB sensing method with large parasitic capacitance is proposed to reduce the time to transfer BL (Bit Line) voltage to DL in the read mode. A new BL switching circuit turning on NMOS switches faster is also proposed. Furthermore, the access time is reduced to 35.63ns from 40ns in the read mode and thus meets the requirement since BL node voltage is clamped at 0.6V by a DL clamping circuit instead of precharging the node to VDD-VT and a differential amplifier are used. The layout size of the designed 512Kb EEPROM memory IP based on a $0.13{\mu}m$ BCD is $923.4{\mu}m{\times}1150.96{\mu}m$ ($=1.063mm^2$).

• Journal of Power Electronics
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• v.18 no.2
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• pp.332-342
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• 2018

This paper proposes a parameter design method for multi-element resonant converters (MERCs) with a unique resonant zero point (RZP). This method is mainly composed of four steps. These steps include program filtration, loss comparison, 3D figure fine-tuning and priority compromise. It features easy implementation, effectiveness and universal applicability for almost all of the existing RZP-MERCs. Meanwhile, other design methods are always exclusive for a specific topology. In addition, a novel dual-CTL converter is also proposed here. It belongs to the RZP-MERC family and is designed in detail to explain the process of parameter selection. The performance of the proposed method is verified experimentally on a 500W prototype. The obtained results indicate that with the selected parameters, an extensive dc voltage gain is obtained. It also possesses over-current protection and minimal switching loss. The designed converter achieves high efficiencies among wide load ranges, and the peak efficiency reaches 96.9%.