• Journal of Industrial Convergence
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• v.19 no.6
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• pp.145-153
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• 2021

This study empirically verified whether there is a dual mediating effect of individual optimistic bias and information security intention in the relationship between information security attitude and information security behavior of social welfare college students. The subjects were 295 college students majoring in social welfare. Spss Process macro was used for analysis. As a result. first there was a significant positive correlation between the variables. Second in the relationship between information security attitude and information security behavior, individual optimistic bias and information security intent each had a simple mediating effect. Third when an individual's optimistic bias and information security intent were simultaneously input, each had a simple mediating effect. Fourth there was a double mediating effect between individual optimistic bias and information security intent. This study provided basic data for the expansion of information security model and information security education of social welfare students.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.10
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• pp.1169-1176
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• 2010

The RF front-end for L1/L2 dual-band Global Positioning System(GPS) receiver is presented in this paper. The RF front-end(down-converter) using low IF architecture consists of a wideband low noise amplifier(LNA), a current mode logic(CML) frequency divider and a I/Q down-conversion mixer with a poly-phase filter for image rejection. The current bleeding technique is used in the LNA and mixer to obtain the high gain and solve the head-room problem. The common drain feedback is adopted for low noise amplifier to achieve the wideband input matching without inductors. The fabricated RF front-end using $0.18{\mu}m$ CMOS process shows a gain of 38 dB for L1 and 41 dB for L2 band. The measured IIP3 is -29 dBm in L1 band and -33 dBm in L2 band, The input return loss is less than -10 dB from 50 MHz to 3 GHz. The measured noise figure(NF) is 3.81 dB for L1 band and 3.71 dB for L2 band. The image rejection ratio is 36.5 dB. The chip size of RF front end is $1.2{\times}1.35mm^2$.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.22 no.1
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• pp.252-264
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• 2023

This paper proposes a design of a dual-band band-pass filter that integrates a λg/2 open SIR structure, a transmission line, and a fork-type structure with symmetric and asymmetric open stubs. To obtain the dual-band effect, the proposed filter uses the SIR structure and adjusts the impedance ratio of the SIR structure. Therefore, the position of the harmonics of the filter is shifted through the adjustment of the impedance ratio, and this can obtain a double-band effect. In order to obtain the dual-band characteristics, the dual-band effect is obtained by inserting a open stub between the SIR structures with the SIR structure divided in half. In addition, the second frequency response is obtained by adjusting the length of the open symmetrical stub in the fork-shaped structure. The asymmetrical open stub in the fork form achieves optimum bandwidth by adjusting the length. Therefore, the first center frequency of the proposed band-pass filter is 5.896 GHz and the bandwidth is 13.6 %. At this time, the measurement results are 0.13 dB and 33.6 dB. The second center frequency is 5.906 GHz and the bandwidth is 13.6 %. At this time, the measurement results are 0.15 dB and 19.8 dB. The reason is that when the impedance ratio (Δ) is higher than 1, the position of the harmonic is shifted to a lower frequency band. However, if the impedance ratio (Δ) is lowered by one step, the position of harmonics will move to a higher frequency band. The function of the filter designed using these characteristics can be obtained from the measurement result. The proposed band-pass filter has no coupling loss and no via energy concentration loss because there is no coupling structure of input/output and no via hole. Therefore, system integration is possible due to its excellent performance, and it is expected that dedicated short-range communication (DSRC) system applications used in traffic communication systems will be possible.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.10 no.12
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• pp.3600-3607
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• 2009

This paper describes the development of a power sensor for wireless signal over the ultra wideband range of 300~3800MHz with the detecting range of 150mW~150W. The proposed power sensor fundamentally has the function of not only detecting wireless power, but recognizing frequency and measuring VSWR. The development of the power sensor is completed through the design of dual directional coupler, design of power detector block which produces DC data using the corresponding RF input power level, and establishment of collecting the exact calibration data. The dual directional coupler has the operating frequency of 300~3800MHz with the 0.085dB of insertion loss, and directivity of 30dB at least at 3800MHz. The developed power sensor has the capability of power sensing with less than 0.25dB of resolution as well as measuring VSWR of 1.17~1.96 under the practical operating situation of very high power up to 150W at 300~3800MHz.

• Journal of Advanced Navigation Technology
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• v.12 no.2
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• pp.100-108
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• 2008

In this paper, the dual-ground, high-gain and broad-band internal antenna has been designed and fabricated for 4th-generation mobile communication applications. The optimized antenna was fabricated using photolithography method. The antenna consist of the patches, antenna and system ground, and a probe. The patch and ground plane were separated by air. In order to prevent the demage due to radiator swaying, the foams(${\varepsilon}_r{\fallingdotseq}1.03$) were used to fix the patches and ground. The conductor for the radiators was 0.05 [mm] thick. The measured input return loss showed less than -10 [dB] at the broadband from 3499 to 4743 [MHz]. It's measured bandwidth was 1244 [MHz]. The radiation patterns measured at 3400, 3600, 3800, 4000 and 4200 [MHz] showed Omni-directional characteristics. The gain in the E-plane and H-plane was 4.7 ~ 6.1 and 2.1 ~ 4.3 [dBi], respectively.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.12
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• pp.2674-2685
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• 1997

In this paper, the design and imprlementation of dual-band power amplifier which is used as a critical part for mobile phone to be simultaneously working at a dual band, 800MHz CDAM and PCS frequency band is described. DC operating point of power FET is limited to Class-B to enable long talk time considering that the tyupical power range of CDMA phones in working is around 10 to Class-B to enable long talk time considering that the typical power range of CDMA phones in working is around 10 to 15dBm, i.e., liner range. The power amplifier which employs two GaAs FETs with good linerity at a low operating point has duplexer cuplexer circuit to separate two frequency bands at input and output stage. Electromagnetic analysis for via holes and coupling between narrow transmission lines is included to design a circuit. Moduld size of 0.96CC($22{\times}14.5{\times}3mm^3$) and maximum module current of 130mA at output power range, 10 to 15dBm are attained. The power amplifer module has achieved ACPR performance with 2 to 3dB marging from IS-95 requirement at output powers, 23.5dBm for PCS and 28dBm for 800MHz CDMA respectively.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.10
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• pp.2339-2344
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• 2014

of a microstrip transmission line, this transmission line can operate as the microstrip line or the coplanar line according to open or short connection between the ungrounded copper plane and grounded plane on the base plane. Two different type operation of the transmission line means that one transmission line can have two different characteristic impedances. This paper proposes and fabricates the circuit to be operated 2-ports power transmission line or 2-way power divider with the stable input matching characteristic by using this dual-impedance transmission line. The proposed circuit operates 2-ports power transmission line in case of the coplanar line or 2-way power divider line in case of the microstrip line. The fabricated circuit shows $S_{21}$ > -0.2 dB and $S_{11}$ < -15 dB above 700 MHz when the circuit operates 2-ports power transmission line. And, it is $S_{21}$ > -3.8 dB, $S_{11}$ < -10 dB and $S_{21}/S_{31}$ < ${\pm}0.3dB$ above 700 MHz when the circuit operates 2-way power divider.

• Journal of Internet of Things and Convergence
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• v.10 no.3
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• pp.19-24
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• 2024

Recent advances in large-scale data processing technologies such as big data, cloud computing, and artificial intelligence have increased the demand for high-performance storage devices in data centers and enterprise environments. In particular, the fast data response speed of storage devices is a key factor that determines the overall system performance. Solid state drives (SSDs) based on the Non-Volatile Memory Express (NVMe) interface are gaining traction, but new bottlenecks are emerging in the process of handling large data input and output requests from multiple hosts simultaneously. SSDs typically process host requests by sequentially stacking them in an internal queue. When long transfer length requests are processed first, shorter requests wait longer, increasing the average response time. To solve this problem, data transfer timeout and data partitioning methods have been proposed, but they do not provide a fundamental solution. In this paper, we propose a dual queue based scheduling scheme (DQBS), which manages the data transfer order based on the request order in one queue and the transfer length in the other queue. Then, the request time and transmission length are comprehensively considered to determine the efficient data transmission order. This enables the balanced processing of long and short requests, thus reducing the overall average response time. The simulation results show that the proposed method outperforms the existing sequential processing method. This study presents a scheduling technique that maximizes data transfer efficiency in a high-performance SSD environment, which is expected to contribute to the development of next-generation high-performance storage systems

• Journal of the Ergonomics Society of Korea
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• v.33 no.3
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• pp.241-253
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• 2014

Objective: The objective of this study was to examine multi-modal interaction effects of input-mode switching on the use of smart phones. Background: Multi-modal is considered as an efficient alternative for input and output of information in mobile environments. However, there are various limitations in current mobile UI (User Interface) system that overlooks the transition between different modes or the usability of a combination of multi modal uses. Method: A pre-survey determined five representative tasks from smart phone tasks by their functions. The first experiment involved the use of a uni-mode for five single tasks; the second experiment involved the use of a multi-mode for three dual tasks. The dependent variables were user preference and task completion time. The independent variable in the first experiment was the type of modes (i.e., Touch, Pen, or Voice) while the variable in the second experiment was the type of tasks (i.e., internet searching, subway map, memo, gallery, and application store). Results: In the first experiment, there was no difference between the uses of pen and touch devices. However, a specific mode type was preferred depending on the functional characteristics of the tasks. In the second experiment, analysis of results showed that user preference depended on the order and combination of modes. Even with the transition of modes, users preferred the use of multi-modes including voice. Conclusion: The order of combination of modes may affect the usability of multi-modes. Therefore, when designing a multi-modal system, the fact that there are frequent transitions between various mobile contents in different modes should be properly considered. Application: It may be utilized as a user-centered design guideline for mobile multi modal UI system.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.2
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• pp.189-197
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• 2014

This work proposes a 12b 100 MS/s $0.11{\mu}m$ CMOS three-step hybrid pipeline ADC for high-speed communication and mobile display systems requiring high resolution, low power, and small size. The first stage based on time-interleaved dual-channel SAR ADCs properly handles the Nyquist-rate input without a dedicated SHA. An input sampling clock for each SAR ADC is synchronized to a reference clock to minimize a sampling-time mismatch between the channels. Only one residue amplifier is employed and shared in the proposed ADC for the first-stage SAR ADCs as well as the MDAC of back-end pipeline stages. The shared amplifier, in particular, reduces performance degradation caused by offset and gain mismatches between two channels of the SAR ADCs. Two separate reference voltages relieve a reference disturbance due to the different operating frequencies of the front-end SAR ADCs and the back-end pipeline stages. The prototype ADC in a $0.11{\mu}m$ CMOS shows the measured DNL and INL within 0.38 LSB and 1.21 LSB, respectively. The ADC occupies an active die area of $1.34mm^2$ and consumes 25.3 mW with a maximum SNDR and SFDR of 60.2 dB and 69.5 dB, respectively, at 1.1 V and 100 MS/s.