• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.10
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• pp.14-22
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• 2010

The source/channel/drain regions are formed by ion implantation with different dopant types of $n^+/p^{(+)}/n^+$ in the fabrication of the conventional n-type metal-oxide-semiconductor field effect transistor(NMOSFET). In implementing the ultra-small devices with channel length of sub-30 nm, in order to achieve the designed effective channel length accurately, low thermal budget should be considered in the fabrication processes for minimizing the lateral diffusion of dopants although the implanted ions should be activated as completely as possible for higher on-current level. Junctionless (JL) MOSFETs fully capable of the the conventional NMOSFET operations without p-type channel for enlarging the process margin are under researches. In this paper, the optimum design of the JL MOSFET based on silicon nanowire (SNW) structure is carried out by 3-D device simulation and the basic radio frequency (RF) characteristics such as conductance, maximum oscillation frequency($f_{max}$), current gain cut-off frequency($f_T$) for the optimized device. The channel length was 30 run and the design variables were the channel doping concentration and SNW radius. For the optimally designed JL SNW NMOSFET, $f_T$ and $f_{max}$ high as 367.5 GHz and 602.5 GHz could be obtained, respectively, at the operating bias condition $V_{GS}$ = $V_{DS}$ = 1.0 V).

• Journal of the Korean Vacuum Society
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• v.22 no.3
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• pp.131-137
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• 2013

The thin insulator films for organic memory device were made by the plasma polymerization method using the styrene monomer which was not the wet process but the dry process. For the formation of stable plasma, we make an effort for controlling the monomer with bubbler and circulator system. The thickness of plasma polymerized styrene insulator layer was 430 nm, the thickness of the Au memory layer was 7 nm thickness of plasma polymerized styrene tunneling layer was 30, 60 nm, the thickness of pentacene active layer was 40 nm, the thickness of source and drain electrodes were 50 nm. The I-V characteristics of fabricated memory device got the hysteresis voltage of 45 V at 40/-40 V double sweep measuring conditions. If it compared with the results of previous paper which was the organic memory with the plasma polymerized MMA insulation thin film, this result was greater than 18 V, the improving ratio is 60%. From the paper, styrene indicated a good charge trapping characteristics better than MMA. In the future, we expect to make the organic memory device with plasma polymerized styrene as the memory thin film.

• Journal of Korean Tunnelling and Underground Space Association
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• v.19 no.3
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• pp.533-549
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• 2017

In this study, drainage systems were proposed to drain the leakage of groundwater in the existing underground concrete structures. The system consists of drainage board, wire mesh, fixed nail, and mortar with mineral. In order to increase constructability, the drainage board and wire mesh were attached on the surface of cement concrete using the air nailer and fixed nail. The mortar with 30% of blast furnace slag was sprayed on the drainage board and wire mesh using the spray mortar equipment. The field test construction was carried out in a conventional concrete lining tunnel and concrete retaining wall for performance verification of the drainage system in the field. There was no problem with performance degradation in the drainage system for three years after construction. The bond strength tests were performed on the sprayed mortar at 14 days and about 3 years after field test construction. In case of attaching the wire mesh on the drainage board, the bond strengths of the sprayed mortar were 1.04 MPa at 14 days and 1.46 MPa about 3 years. In case of the drainage board without the wire mesh, the bond strengths of the sprayed mortar were 1.13 MPa at 14 days and 0.89 MPa, less than 1 MPa of bond strength criteria, about 3 years.

• Journal of IKEEE
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• v.11 no.4
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• pp.272-278
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• 2007

In this paper, we report on the 2D (two-dimensional) simulation result of the DC (direct current) electrical and thermal characteristics of AlGaN/GaN HEMTs (high electron mobility transistors) grown on Si substrate, in comparison with those grown on sapphire and SiC (silicon carbide) substrate, respectively. In general, the electrical properties of HEMT are affected by electron mobility and thermal conductivity, which depend on substrate material. For this reason, the substrates of GaN-based HEMT have been widely studied today. The simulation results are compared and studied by applying general Drift-Diffusion and thermal model altering temperature as 300, 400 and 500 K, respectively. With setting T=300 K and $V_{GS}$=1 V, the $I_{D,max}$ (drain saturation current) were 189 mA/mm for sapphire, 293 mA/mm for SiC, and 258 mA/mm for Si, respectively. In addition, $G_{m,max}$ (maximum transfer conductance) of sapphire, SiC, Si was 38, 50, 31 mS/mm, respectively, at T=500 K.

• Journal of Korean Society on Water Environment
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• v.31 no.1
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• pp.12-18
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• 2015

In this research, the hydrologic effects between a pre-existing urban landuse and low impact development (LID) applied conditions were compared and evaluated. The infiltration trench and tree box filter that were utilized in LID represent only 1% of the catchment area that they drain. Storm event monitoring were conducted from July 2010 to July 2014 on a total of 22 storm events in both LID sites. After LID, hydrological improvement was observed as the sites exhibited a delay (lag time) or reduction in the magnitude, frequency and duration of runoff and flow peaks as the rainfall progress. In addition, the maximum irreducible peak flow reduction for infiltration trench was found to be 61% and 33% for the tree box filter when rainfall was 40 mm and 30 mm, respectively. In designing LID, it is recommended to consider the storage capacity and catchment area, as well as the amount of rainfall and runoff on the site.

• Resources Recycling
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• v.18 no.3
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• pp.11-19
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• 2009

Recently the problem of global environment is became by social issue. Accordingly the interests to recycling and saving of resources are growing from daily life to varieties field of industry. To preserve the global environment, prevent global warming, environmental destruction, environmental pollution by wastes, the drain of aggregate, plasticity energy of cement and decrease in carbon dioxide are an urgent problem that must be resolved. So there is to a field of building industry and stands but on the inside of the building the many double meaning resources usefully, applies. Also the seller masterpiece building where the service life is long planned is safe and comfortably, maintenance, suppresses the construction which is not necessary is unnecessary. Also the seller masterpiece building where the service life is long planned is safe and comfortably, maintenance, suppresses the construction which is not necessary is unnecessary. By revitalizing effective use of limited earth resources, recycling and controling production of construction waste, this study introduced to a method for Long-Term Durability of Construction Structure and Effective Use of Technology for Construction Waste considering architectural demand and earth environment. It is for reduction of an earth environment load from the side of construction production and performance design of a structure.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.19 no.11
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• pp.1193-1203
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• 2008

An active antenna(AA) can have wider bandwidth and more gain with small antenna size than those of passive antennas. However, AA inherently generates thermal noise and spurious signals from an active device. Moreover, the spurious performance of AA is very important in a highly sensitive receiving system since it is located at the front end of the receiving system. In this study, we developed an AA with $100{\sim}500\;MHz$, having the output P1dB higher than 3 dBm and little spurious signals in real environments. To achieve such performance, we designed an AA with 3-stage amplifier using CD(common drain) FET and 2 BJTs. Its electrical performances were simulated using ADS. The measurement results for typical gain, NF, OIP3, VSWR and P1dB in the required frequency band were 9.7 dBi, 10 dB, 14 dBm, 1.7:1 and 3 dBm respectively. They are in good agreement with simulation results. The unwanted spectrum level of the proposed AA is $10{\sim}30\;dB$ lower than that of the antenna with CS(common source) FET configuration at a west suburban area of Seoul, which shows that the proposed AA can be applicable to a highly sensitive receiving system for detecting unknown weak signals mixed with broadcasting and civilian communication signals.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.10 no.12
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• pp.3626-3631
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• 2009

This study has provided some of the first experimental results of NMOSFET hot-carrier degradation for the analog circuit application. After hot-carrier stress under the whole range of gate voltage, the degradation of NMOSFET characteristics is measured in saturation region. In addition to interface states, the evidences of hole and electron traps are found near drain depending on the biased gate voltage, which is believed to the cause for the variation of the transconductance($g_m$) and the output conductance($g_{ds}$). And it is found that hole trap is a dominant mechanism of device degradation in a low-gate voltage saturation region, The parameter degradation is sensitive to the channel length of devices. As the channel length is shortened, the influence of hole trap on the channel conductance is increased. Because the magnitude of $g_m$ and $g_{ds}$ are increased or decreased depending on analog operation conditions and analog device structures, careful transistor design including the level of the biased gate voltage and the channel length is therefore required for optimal voltage gain ($A_V=g_m/g_{ds}$) in analog circuit.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.1
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• pp.38-46
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• 1999

o.25${\mu}m$ T-shaped gate P-HEMT is fabricated and used for design of X0band three stage monolithic microwave integrated circuit(MMIC) low noise amplifier(LNA). The fabricated P-HEMT exhibits an extrinsis transconductance of 400mS/mm and a drain current of 400mA/mm. The RF and noise characteristics show that the current gain cut off frequency is 65GHz and minimum noise figure(NFmin) of 0.7dB with an associated gain of 14.8dB at 9GHz. In the design of the three stage LNA, we have used the inductive series feedback circuit topology with the short stub. The effects of series feedback to the noise figure, the gain, and the stability have been investigated to find the optimal short stub length. The designed three staage LNA showed a gain of above 33dB, a noise figure of under 1.2dB, and ainput/output return loss of under 15dB and 14dB, respectively. The results show that the fabricated P-HEMT is very suitable for a X-band LNA with high gain.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.10
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• pp.33-46
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• 2015

In this paper, we predicts the analog and digital circuit performance of FinFETs that are scaled down following the ITRS(International technology roadmap for semiconductors). For accurate prediction of the circuit performance of scaled down devices, accurate parasitic resistance and capacitance analytical models are developed and their accuracies are within 2 % compared to 3D TCAD simulation results. The parasitic capacitance models are developed using conformal mapping, and the parasitic resistance models are enhanced to include the fin extension length($L_{ext}$) with respect to the default parasitic resistance model of BSIM-CMG. A new algorithm is developed to fit the DC characteristics of BSIM-CMG to the reference DC data. The proposed capacitance and resistance models are implemented inside BSIM-CMG to replace the default parasitic model, and SPICE simulations are performed to predict circuit performances such as $f_T$, $f_{MAX}$, ring oscillators and common source amplifier. Using the proposed parasitic capacitance and resistance model, the device and circuit performances are quantitatively predicted down to 5 nm FinFET transistors. As the FinFET technology scales, due to the improvement in both DC characteristics and the parasitic elements, the circuit performance will improve.