• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.9
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• pp.41-45
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• 2014

In this paper, a high-efficiency power amplifier is implemented by using a drain bias control circuit operated at low input power for WPT(Wireless Power Transfer). Adaptive bias control circuit was added to high-efficiency class-E amplifier. It was possible to obtain the overall improvement in efficiency by adjusting the drain bias at low input power. The proposed adaptive class-E amplifier is implemented by using the input and output matching network and serial resonant circuit for improvement in efficiency. Drain bias control circuit consists of a directional coupler, power detector, and operational amplifier for adjusting the drain bias according to the input power. The measured results show that output powers of 41.83 dBm were obtained at 13.56 MHz. At this frequency, we have obtained the power added efficiency(PAE) of 85.67 %. It was confirmed increase of PAE of an average of 8 % than the fixed bias from the low input power level of 0 dBm ~ 6 dBm.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.2
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• pp.185-190
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• 2016

A 70-${\AA}$ nanowire field-effect transistor (FET) for sub-10-nm CMOS technology is designed and simulated in order to investigate the impact of an oxide trap on random telegraph noise (RTN) in the device. It is observed that the drain current fluctuation (${\Delta}I_D/I_D$) increases up to a maximum of 78 % due to the single electron trapping. In addition, the effect of various trap positions on the RTN in the nanowire FET is thoroughly analyzed at various drain and gate voltages. As the drain voltage increases, the peak point for the ${\Delta}I_D/I_D$ shifts toward the source side. The distortion in the electron carrier density and the conduction band energy when the trap is filled with an electron at various positions in the device supports these results.

• Proceedings of the KIEE Conference
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• 1996.07c
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• pp.1582-1584
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• 1996

The polycrystalline silicon thin film transistors (poly-Si TFT) are the most promising candidate for active matrix liquid crystal displays (AMLCD) for their high mobilities and current driving capabilities. The leakage current of the poly-Si TFT is much higher than that of the amorphous-Si TFT, thus larger storage capacitance is required which reduces the aperture ratio fur the pixel. The offset gated poly-Si TFTs have been widely investigated in order to reduce the leakage current. The conventional method for fabricating an offset device may require additional mask and photolithography process step, which is inapplicable for self-aligned source/drain ion implantation and rather cost inefficient. Due to mis-alignment, offset devices show asymmetric transfer characteristics as the source and drain are switched. We have proposed and fabricated a new offset poly-Si TFT by applying photoresist reflow process. The new method does not require an additional mask step and self-aligned ion implantation is applied, thus precise offset length can be defined and source/drain symmetric transfer characteristics are achieved.

• Journal of the Korean Geosynthetics Society
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• v.4 no.4
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• pp.39-46
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• 2005

A series of numerical analyses on soft clay ground improved by plastic board drain(PBD) were carried out, in order to investigate the consolidation behavior considering viscosity of the improved ground. The applicability of numerical analyses, in which an elasto-viscoplastic three-dimensional consolidation finite element method is applied in this study, was confirmed through comparison between experimental and analytical results. As the analytical results, consolidation behavior of both settlement and excess pore pressure and effective stress in clay were elucidated. Then secondary consolidation characteristics of improved ground were estimated through compare with results of typical one-dimensional consolidation analysis.

• Proceedings of the Korean Geotechical Society Conference
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• 2010.09b
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• pp.3-12
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• 2010

Vertical drains have been commonly used to increase the rate of the consolidation of dredged material. The installation of vertical drains additionally provides a radial flow path in the dredged foundation. The objective of this study develops a numerical model for 2-D axisymmetric non-linear finite strain consolidation considering self-weight consolidation to predict the effect of vertical drain in dredged foundation which is in process of self-weight consolidation. The non-linear relationship between the void ratio and effective stress and permeability during consolidation are taken into account in the numerical model. The results of the numerical analysis are compared with that of the self-weight consolidation test in which an artificial vertical drain is installed. In addition, the numerical model developed in this paper is the simplified analytical method proposed by Ahn et, al (2010). The comparisons show that the developed numerical model can properly simulate the consolidation of the dredged material with the vertical drains installed.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.26 no.6
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• pp.593-596
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• 2015

In this paper, we design a high efficiency class E power amplifier operating at low drain bias voltage for wireless power transfers. A 13.56 MHz power amplifier is designed at drain bias voltage of 12.5 V using Si MOSFET with the breakdown voltage of 40 V. High quality-factor solenoidal inductor is designed and fabricated for use in output matching circuit to improve output power and efficiency. Input matching circuit simply consists of resistor and inductor to reduce the circuit area and improve the stability. The fabricated power amplifier shows the measured output power of 38.6 dBm with the gain of 16.6 dB and power added efficiency of 89.3 % at 13.56 MHz.

• Geomechanics and Engineering
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• v.7 no.1
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• pp.105-131
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• 2014

In this paper, the effects of variability of smear zone characteristics induced by installation of prefabricated vertical drains on the preloading design are investigated employing analytical and numerical approaches. Conventional radial consolidation theory has been adopted to conduct analytical parametric studies considering variations of smear zone permeability and extent. FLAC 2D finite difference software has been employed to conduct the numerical simulations. The finite difference analyses have been verified using three case studies including two embankments and a large-scale laboratory consolidometer with a central geosynthetic vertical drain. A comprehensive numerical parametric study is conducted to investigate the influence of smear zone permeability and extent on the model predictions. Furthermore, the construction of the trial embankment is recommended as a reliable solution to estimate accurate smear zone properties and minimise the post construction settlement. A back-calculation procedure is employed to determine the minimum required waiting time after construction of the trial embankment to predict the smear zone characteristics precisely. Results of this study indicate that the accurate smear zone permeability and extent can be back-calculated when 30% degree of consolidation is obtained after construction of the trial embankment.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.11a
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• pp.171-172
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• 2007

We fabricated the metal-ferroelectric-insulator-semiconductor filed-effect transistors (MFIS-FETs) using the $(Bi,La)_4Ti_3O_{12}\;and\;LaZrO_x$ thin films. The $LaZrO_x$ thin film had a equivalent oxide thickness (EOT) value of 8.7 nm. From the capacitance-voltage (C-V) measurements for an Au/$(Bi,La)_4Ti_3O_{12}/LaZrO_x$/Si MFIS capacitor, a hysteric shift with a clockwise direction was observed and the memory window width was about 1.4 V for the bias voltage sweeping of ${\pm}9V$. From drain current-gate voltage $(I_D-V_G)$ characteristics of the fabricated Fe-FETs, the obtained threshold voltage shift (memory window) was about 1 V due to ferroelectric nature of BLT film. The drain current-drain voltage $(I_D-V_D)$ characteristics of the fabricated Fe-FETs showed typical n-channel FETs current-voltage characteristics.

• Geotechnical Engineering
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• v.16 no.1
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• pp.56-57
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• 2000

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.4
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• pp.21-27
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• 2009

In this work, Er-silicided SB-SOI nMOSFET and Pt-silicided SB-SOI pMOSFET have been fabricated to investigate the current-voltage characteristics of Schottky barrier SOI nMOS and pMOS at elevated temperature. The dominant current transport mechanism of SB nMOS and pMOS is discussed using the measurement results of the temperature dependence of drain current with gate voltages. It is observed that the drain current increases with the increase of operating temperature at low gate voltage due to the increase of thermal emission and tunneling current. But the drain current is decreased at high gate voltage due to the decrease of the drift current. It is observed that the ON/Off current ratio is decreased due to the increased tunneling current from the drain to channel region although the ON current is increased at elevated temperature. The threshold voltage variation with temperature is smaller and the subthreshold swing is larger in SB-SOI nMOS and pMOS than in SOI devices or in bulk MOSFETs.