• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.132.2-132.2
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• 2014

란탄족 원소가 도핑된 세라믹 나노결정, 즉, 나노형광체는 도핑되는 원소의 종류에 따라 다양한 색을 발광할 수 있다. 일반적으로 형광체는 외부에너지에 의해 여기된 후 흡수한 에너지 보다 작은 에너지의 가시광을 발광하게 된다. 이러한 현상은 downconversion 발광으로 알려져 있다. 그러나 모체에 Yb3+와 Er3+를 도핑하는 경우 적외선을 흡수하여 가시광선을 발광하는 upconversion 현상이 관찰된다. Upconversion 형광체를 이용하여 적외선을 가시광으로 변환시키면 sub-band gap 손실을 줄임으로써 태양전지 효율을 높일 수 있고, 바이오 이미징 감도를 높일 수도 있다. 그러나, upconversion 발광기구에서는 두 개의 적외선 광자가 흡수되어 하나의 가시광 광자가 방출되기 때문에 upconversion 발광 효율은 downconversion 발광 효율에 비하여 매우 낮은 특성을 보인다. 특히 형광체의 크기가 작아져 나노미터 영역의 크기가 되면 효율이 더욱 낮아지기 때문에 upconversion 나노형광체의 경우 효율을 증가시키기 위하여 형광체 주위로 결정질 쉘을 형성시키는 것이 필요하다. 이 때, 결정질 쉘에 downconversion 특성을 보일 수 있는 란탄족 원소를 도핑하는 경우 upconversion 발광 강도가 증대될 뿐 아니라, 하나의 나노입자에서 upconversion과 downconversion 두 가지 서로 다른 발광 특성을 관찰할 수 있다. 본 발표에서는 단일 나노입자에서 upconversion과 downconversion 발광을 보이는 이중발광 코어/쉘 나노형광체의 발광 특성에 대하여 논의하고자 한다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.9C
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• pp.913-921
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• 2005

A complex bandpass sampling technique can provide a more flexible architecture for designing a software- defined radio(SDR) system, because it has several advantageous features of larger sampling range and lower minimum sampling frequency than a real bandpass sampling method. In spite of the potential advantages of the complex bandpass sampling, solid investigation for the direct downconversion of multiple signals by the complex sampling theory has not been reported yet. Thus, we propose in this paper a novel scheme for the downconversion of multiple signals using the complex bandpass sampling, and develop the formulae related to the complex bandpass sampling for practical usage, such as the valid sampling range, the intermediate frequency (If), and the minimum sampling frequency of the downconversion of multiple RE signals. Such derived formulae are verified from simulations.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2002.11a
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• pp.54-58
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• 2002

This paper describes the theoretical analysis and performance of a 2.4㎓ bulk-driven downconversion mixer, where the LO signal is input via the bulk. A mixer core designed with a 0.18$\mu\textrm{m}$ CMOS process is able to operate under 0.8V∼1V supply voltage. The RF, LO, and IF port frequencies are 2.45㎓, 2.4㎓, and 50MHz, respectively. The measurement results exhibit conversion gain of -1.8㏈, l㏈ compression point of -17㏈m and IIP3 of -4㏈m with 0㏈m LO power. The power consumption is as small as 4mW.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2002.11a
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• pp.77-81
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• 2002

This paper demonstrates a CMOS downconversion mixer for 2.4GHz ISM band applications. The mixer, implemented in a 0.18um CMOS process, is based on the CMOS Gilbert Cell mixer, With a 2.5GHz local oscillator and a 2.45GHz RF input, the measurement results exhibit power conversion gam of -6dB, IIP3 of -6dBm, input $P_{-1dB}$ of -15 dBm, and power dissipation in mixer core of 2.7 mW with 0㏈m LO power and 1.8V supply voltage.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2003.11a
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• pp.91-95
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• 2003

In this work, we have designed Gilbert cell downconversion mixer using 0.25um Anam CMOS process, we also have analyzed Conversion gain and IIP3 using Taylor series in our own unique way. Especially, bulk terminal is used as LO( Local Oscillator) input for reduction of power consumption and supply voltage. Supply voltage used in this design is lower than 1.8V and core current is less than 500uA. The simulation experiments showed that the conversion gain, IIP3, and power consumption were -1dB, 4.46dBm, and 0.8mW, respectively.

• Proceedings of the IEEK Conference
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• 2003.11c
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• pp.391-395
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• 2003

In this work, we have designed Gilbert cell downconversion mixer using 0.25um Anam CMOS process, we also have analyzed Conversion gain and IIP3 using Taylor series in our own unique way. Especially, bulk terminal is used as LO( Local Oscillator) input for reduction of power consumption and supply voltage. Supply voltage used in this design is lower than 1.8V and core current is less than 500uA. The simulation experiments showed that the conversion gain, IIP3, and power consumption were -1 dB, 4.46dBm, and 0.8mW, respectively.

• Journal of Advanced Navigation Technology
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• v.13 no.1
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• pp.48-53
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• 2009

The CMOS RF front-end for Global Positioning System(GPS)are implemented in 1P8M CMOS $0.13{\mu}m$ process. The LNAs consist of LNA1 with high gain and low NF, and LNA2 with low gain and high IIP3 for supporting operation with active and passive antenna. the measured performances of both LNAs are 16.4/13.8 dB gain, 1.4/1.68 dB NF, and -8/-4.4 dBm IIP3 with 3.2/2 mA form 1.2 V supply, respectively. The quadrature downconversion mixer is followed by transimpedance amplifier with gain controllability from 27.5 to 41 dB. The front-end performances in LNA1 mode are 39.8 dB conversion gain, 2.2 dB NF, and -33.4 dBm IIP3 with 6.6 mW power consumption.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.5
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• pp.595-604
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• 2016

Utilizing a standard 130-nm CMOS process, a RF frontend is designed at 24 GHz for automotive collision avoidance radar application. Single IF direct conversion receiver (DCR) architecture is adopted to achieve high integration level and to alleviate the DCR problem. The proposed frontend is composed of a two-stage LNA and downconversion mixers. To save power consumption, and to enhance gain and linearity, stacked NMOS-PMOS $g_m$-boosting technique is employed in the design of LNA as the first stage. The switch transistors in the mixing stage are biased in subthreshold region to achieve low power consumption. The single balanced mixer is designed in PMOS transistors and is also realized based on the well-known folded architecture to increase voltage headroom. This frontend circuit features enhancement in gain, linearity, and power dissipation. The proposed circuit showed a maximum conversion gain of 19.6 dB and noise figure of 3 dB at the operation frequency. It also showed input and output return losses of less than -10 dB within bandwidth. Furthermore, the port-to-port isolation illustrated excellent characteristic between two ports. This frontend showed the third-order input intercept point (IIP3) of 3 dBm for the whole circuit with power dissipation of 6.5 mW from a 1.5 V supply.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.12C
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• pp.1249-1256
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• 2006

This paper proposes, based on a bandpass sampling theory, a novel method to find valid sampling frequency range and minimum sampling rate with low computational complexity for downconversion of multiple bandpass radio frequency (RF) signals. Guard-bands or spacing between adjacent downconverted signal spectrums are also taken into consideration in determining sampling frequency for practical implementation. Moreover, we verify through comparison with other method that the proposed method has more advantageous properties.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.7C
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• pp.687-695
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• 2005

A bandpass sampling technique, which is a method directly downconverting a bandpass signal to a baseband or a low IF signal without analog mixers, can be an alterative choice for the SDR system to minimize the RF front-end. In this paper, a complex bandpass sampling technique for two bandpass-filtered signals is proposed. We derived generalized formulae for the available sampling range, the signal's IF and the minimum sampling frequency taking into consideration the guard-bands for the multiple RE signals. Thru the simulation experiments, the advantages of the . complex bandpass sampling over the pre-reported real bandpass sampling are investigated for applications in the SDR design.