• Journal of the Korea Academia-Industrial cooperation Society
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• v.11 no.12
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• pp.4984-4990
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• 2010

In this paper, a Step-down CMOS DC-DC Converter using low power switched capacitor method is designed in a 0.5 ${\mu}m$ technology for the integration of devices. Conventional DC-DC converter is used inductor that can store energy in a magnetic field but have low efficiency because power consumption is caused by magnetic flux. And there were problems with size, weight and price to integrate chip. In this paper, a proposed Inductorless step-down CMOS DC-DC converter of low power using SC method is designed in a 0.5um technology to solve these problems. Designed DC-DC converter have 96% power efficiency with 200kHz frequency by using cadence simulation.

• Journal of Power Electronics
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• v.16 no.5
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• pp.1629-1638
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• 2016

Differential power processing (DPP) systems are among the most effective architectures for photovoltaic (PV) power systems because they are highly efficient as a result of their distributed local maximum power point tracking ability, which allows the fractional processing of the total generated power. However, DPP systems require a high-efficiency, high step-up/down bidirectional converter with broad operating ranges and galvanic isolation. This study proposes a single, magnetic, high-efficiency, high step-up/down bidirectional DC-DC converter. The proposed converter is composed of a bidirectional flyback and a bidirectional isolated switched-capacitor cell, which are competitively cheap. The output terminals of the flyback converter and switched-capacitor cell are connected in series to obtain the voltage step-up. In the reverse power flow, the converter reciprocally operates with high efficiency across a broad operating range because it uses hard switching instead of soft switching. The proposed topology achieves a genuine on-off interleaved energy transfer at the transformer core and windings, thus providing an excellent utilization ratio. The dynamic characteristics of the converter are analyzed for the controller design. Finally, a 240 W hardware prototype is constructed to demonstrate the operation of the bidirectional converter under a current feedback control loop. To improve the efficiency of a PV system, the maximum power point tracking method is applied to the proposed converter.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.15 no.3
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• pp.1700-1706
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• 2014

In this paper, a step down converter for LED backlight of mobile application has been proposed. The converter which is operated with 4 MHz high switching frequency is capable of reducing mounting area of passive devices consists of a power stage and a control block. Circuit elements of the power stage are inductor, output capacitor, MOS transistors and feedback resistors. The control block consists of pulse width modulator, error amplifier and oscillator etc. Proposed step down converter has been designed and verified using a $0.35{\mu}m$ 1-poly 4-metal BCD process technology. Simulation results show that the output voltage is 1.8 V in 3.7 V input voltage, output current 100 mA which is larger than 25 ~ 50 mA in conventional 500 KHz driven converter when the duty ratio is 0.4.

• Journal of Power Electronics
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• v.13 no.2
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• pp.214-222
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• 2013

This paper proposes a high efficiency step-down flyback converter using a coaxial-cable coupled-inductor which has a higher primary-secondary flux linkage than sandwich winding transformers. The structure of the two-winding coaxial cable transformer is described, and the coupling coefficient of the coaxial cable transformer and that of a sandwich winding transformer are compared. A circuit model of the proposed transformer is also obtained from the frequency-response curves of the secondary short-circuit and of the secondary open-circuit. Finally, the performance of the proposed transformer is validated by the experimental results from a 35W single-output flyback converter prototype. In addition, the proposed two-winding coaxial transformer is extended to a multiple winding coaxial application. For the performance evaluation of the extended version, 35W multi-output hardware prototype of the DC-DC flyback converter was tested.

• Proceedings of the KIPE Conference
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• 2008.06a
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• pp.234-237
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• 2008

This paper deals with a new single-phase Z-source matrix converter (SZMC) topology. Unlike other conventional configurations, the proposed SZMC is not only a step-up frequency converter but also a step-down frequency converter and a voltage boost capability. Thus, the proposed SZMC is also called a frequency step-up/down and voltage step-up converter. A safe-commutation strategy is used in SZMC as free-wheeling operation to eliminate voltage spikes on switches. The operating principles and experimental results of the proposed SZMC are presented.

• Proceedings of the KIEE Conference
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• 2002.07d
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• pp.2589-2591
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• 2002

송수신기의 방식에는 직접변환 방식과 기저대역 신호와 LO(Local Oscillator)를 혼합하여 interpolation 기법을 사용하여 중간 주파수 단계까지 up conversion을 하고 두 번째 LO와 IF신호를 혼합하여 RF신호로 변환하여 송신하는 헤테로다인 방식이 존재한다. 본 논문에서는 이런 송수신기 방식 중에서 헤테로다인 방식을 적용하여 QPSK에서의 digital up /down converter를 Simulink 환경에서 설계 및 구현하였다. Up converter는 4배의 interpolation 필터와 4단짜리 cascaded integrate-comb(CIC)필터를 사용하여 입력데이터의 샘플 레이트를 클럭 레이트까지 증가시켰으며, numerically controlled oscillator (NCO)와 mixer를 사용하여 신호를 변조하였다. Down converter의 구조는 up converter와 동일하며 단지 up converter의 반대순서로 구성되어있다. 이런 모든 과정을 Simulink를 이용한 시뮬레이션과 스펙트럼 분석기를 사용하여 검증해 보았다.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.37 no.5
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• pp.115-123
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• 2000

In this paper, a block FIR(Finite Impulse Response) filtering architecture is proposed for IF digital down converter. Digital down converter consists of digital mixers. decimation filters and down samplers. In this proposed structure, it is shown that a efficient parallel decimation filter architecture can be produced by cancellation of inherent up sampling of the block filter and following down sampler Furthermore. it is shown that computational complexity of the proposed architecture is reduced by exploiting the block FIR structure and zero values of the digital mixers.

• Proceedings of the KIPE Conference
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• 2008.06a
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• pp.34-36
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• 2008

This paper is given a full detail of mathematical analyses of input current for novel active type power factor correction(PFC) AC-DC converter of step up-down added electric isolation. These are compared with harmonics components of input current for a conventional PFC converter of electric isolation type. The proposed PFC converter is constructed in using a new loss-less snubber circuit to achieve a soft switching of control device. Also the proposed converter for discontinuous conduction mode(DCM) eliminates the complicated circuit control requirement and reduces the size of components. The input current waveform in the proposed converter is got to be a sinusoidal form of discontinuous pulse in proportion to magnitude of ac input voltage under the constant duty cycle switching. Therefore, input power factor is nearly unity and the control method is simple. Particularly, the stored energy of loss-less snubber capacitor is recovered with input side and increases input current from resonant operation. The result is that input power factor of the proposed converter is higher than that of a conventional PFC converter. Some simulative results on computer and experimental results are included to confirm the validity of the analytical results.

• ETRI Journal
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• v.26 no.6
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• pp.555-559
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• 2004

We propose an efficient digital IF down converter architecture for dual-mode WCDMA/cdma2000 based on the concept of software defined radio. Multi-rate digital filters and fractional frequency conversion techniques are adopted to implement the front end of a dual-mode receiver for WCDMA and cdma2000. A sub-sampled digital IF stage was proposed to support both WCDMA and cdma2000 while lowering the sampling frequency. Use of a CIC filter and ISOP filter combined with proper arrangement of multi-rate filters and common filter blocks resulted in optimized hardware implementation of the front end block in 292k logic gates.

• Proceedings of the Korean Society of Marine Engineers Conference
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• 2005.06a
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• pp.304-309
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• 2005

This paper presents an electronic ballast using a step down converter, a low frequency inverter for high intensity short-arc discharge lamp. The proposed ballast is composed of a full-wave rectifier, a step down converter operated as a current source with power regulation and a low frequency inverter with external ignition circuit. The ignition circuit generates high voltage pulse of $3{\sim}5[kV]$ peak, 130[Hz] periodically. Moreover, it is able to reignite at regular intervals by protective circuit. As experimental results on the test, acoustic resonance phenomenon is eliminated by operating the low frequency square wave voltage and current. Lamp voltage, current and consumption power are measured 123.8[V], 8.1[A] and 1,002[W], respectively. It was confirmed that the designed ballast operate the lamp with a constant power.