• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.8
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• pp.1774-1781
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• 1997

In this paper, we propose a full digital frequency and phase locked loop for CATV and HDTV receivers adopting VSB modulation. The CATV and HDTV receivers proposed by the Grand-Alliance in USA are ultilizing analog signal processing technology for carrier recovery. By the way, it is not a good architecture for the development of single chip ASIC operating in digital domain. To solve this problem while improving the performance, we first down convert the received r.f. signal to a near baseband signal for a low-rate AD converter and then we use digital signal processing techniques. The proposed system has the frequency pull-in range of -200 KHz +2.50 KHz. Moreover, it has the ability of adaptive loop bandwidth control according to the amount of frequency offset to improve the acquisition time while reducing the phase noise.

• Journal of the Korea Institute of Military Science and Technology
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• v.24 no.1
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• pp.50-60
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• 2021

For conventional AESA radars, DC-DC power modules using 300 Vdc have low efficiency, high volume, heavy weight, and high price, which have problems in modularity with T/R module groups. In this paper, to improve these problems, we propose a distributed DC-DC power module with high-voltage 800 Vdc and high-efficiency Step-down Converter. In particular, power requirements for modern and future marine weapons systems and sensors are rapidly evolving into high-energy and high-voltage power systems. The power distribution of the next generation Navy AESA radar antenna is under development with 1000 Vdc. In this paper, the proposed highvoltage, high-efficiency DC-DC power modules increase space(size), weight, power and cooling(SWaP-C) margins, reduce integration costs/risk, and reduce maintenance costs. Reduced system weight and higher reliability are achieved in navy and ground AESA systems. In addition, the proposed architecture will be easier to scale with larger shipboard radars and applicable to other platforms.

• Journal of IKEEE
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• v.16 no.1
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• pp.28-33
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• 2012

Recently, with mobile devices increasing, as a variety of multimedia functions are needed, battery life is decreased. Accordingly the methods for extending the battery life has been proposed. In order to implement these methods, we have to know exactly the status of the battery, so we need a high resolution analog to digital converter(ADC). In case of the existing integrating sigma-delta ADC, it have not convert reset-time conversion cycle to function of resolution. Because of this reason, all digital values corresponding to the all number of bits will not be able to be expressed. To compensated this drawback, this paper propose that all digital values corresponding to the number of bits can be expressed without having to convert reset-time additional conversion cycle to function of resolution by using a up-down counter. The proposed circuit achieves improved SNDR compared to conventional converters simulation result. Also, this was designed for low power suitable for battery management systems and fabricated in 0.35um process.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.11
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• pp.21-30
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• 1998

In this paper, a digital current control system using a FPGA(Field Programmable Gate Array) was implemented, and the system was applied to an induction motor widely used as an industrial driving machine. The FPGA designed by VHDL(VHSIC Hardware Description Language) consists of a PWM(Pulse Width Modulation) generation block, a PWM protection block, a speed measuring block, a watch dog timer block, an interrupt control block, a decoder logic block, a wait control block and digital input and output blocks respectively. Dedicated clock inputs on the FPGA were used for high-speed execution, and an up-down counter and a latch block were designed in parallel, in order that the triangle wave could be operated at 40 MHz clock. When triangle wave is compared with many registers respectively, gate delay occurs from excessive fan-outs. To reduce the delay, two triangle wave registers were implemented in parallel. Amplitude and frequency of the triangle wave, and dead time of PWM could be changed by software. This FPGA was synthesized by pASIC 2SpDE and Synplify-Lite synthesis tool of Quick Logic company. The final simulation for worst cases was successfully performed under a Verilog HDL simulation environment. And the FPGA programmed for an 84 pin PLCC package was applied to digital current control system for 3-phase induction motor. The digital current control system of the 3 phase induction motor was configured using the DSP(TMS320C31-40 MHz), FPGA, A/D converter and Hall CT etc., and experimental results showed the effectiveness of the digital current control system.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.40 no.7
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• pp.293-299
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• 2003

In this paper, we have proposed a high conversion and isolation characteristic V-band quadruple sub-harmonic mixer monolithic circuit which is designed and fabricated for the millimeter wave down converter applications. While most of the sub-harmonic mixers use a half of fundamental frequency, we adopt a quarter of the fundamental frequency. The proposed circuit is based on a sub-harmonic mixer with APDP(anti-parallel diode pair) and the 0.1 ${\mu}{\textrm}{m}$ PHEMT's (pseudomorphic high electron mobility transistors). Lumped elements at IF port provide better selectivity of IF frequency and increase isolation. Maximum conversion gain of 0.8 ㏈ at a LO frequency of 14.5㎓ and at a RF frequency of 60.4 ㎓ is measured. Both LO-to-RF and LO-to-IF isolations are higher than 50 ㏈. The conversion gain and isolation characteristic are the best performances among the reported quadruple sub-harmonic mixer operating in the V-band millimeter wave frequency thus far.

• Progress in Medical Physics
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• v.13 no.2
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• pp.55-61
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• 2002

In this work, EPM (effective point of measurement) of parallel plate ionization chamber with three different spacing were investigated. If the plate separation is less than 2 mm one generally assumes that the effective point of measurement is just behind the front window of the parallel plate ionization chamber. For chamber with relatively large separation, such as the ones used for very accurate exposure measurements, this assumption breaks down and the EPM depends on plate separation and thickness of the front window. For parallel plate chambers, conventional theoretical analyses suggest that the EPM is the inner front wall and that it shifts towards the geometric centre of the chamber as the plate separation increases. The PP-IC (parallel plate ionization chamber) is fabricated using acrylic plate for the chamber medium and printed circuit board for electrical configuration. The various sizes of the sensitive volumes designed so far are 0.9, 1.9, and 3.1 cc. The gap between two electrodes ranges from 3, 6, and 10mm. Also the charge-to-voltage converter is designed to collect the electrons produced in the ionization chamber cavity. As the result of our experiment, the EPM shift was within 0.6 mm in photon beams and 0.4 mm to 2.5 mm in electron beams for the plate separation of 6 mm and 10 mm. EPM shifts towards the geometric center of the chamber as the plate separation increases.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.11C
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• pp.1085-1097
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• 2009

We present a structure and design method of the D8PSK modem compatible with the VDL mode-2 standard and performance test results of the developed modem. In VDL mode-2, the raised cosine filter is used only in the transmitter and a general low pass filter is used in the receiver. Consequently, we can not achieve ISI reduction but can have better spectrum characteristics. Although there is 1~2 dB performance degradation with an un-matched filter compared to that with a matched filter, it is more important to minimize adjacent channel interference in narrow band communications. The transmit signal is generated digitally to avoid the problems(I/Q imbalance and DC offset etc.) of analog modulators. In addition the digital down converter using digital IF sampling technique is adopted for the receiver. This paper contains the overall configuration, design method and simulation results based in part on the previously proposed structures and algorithms. It is confirmed that the modem transmits and receives messages successfully at a speed of max. 870 km/h over ranges of up to 310 km through the ground and in-flight communication tests.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.18 no.1 s.116
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• pp.37-43
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• 2007

In this.paper, we introduce design and implementation results of the single balanced diode mixer for European point-to-point microwave radio in order to improve flatness performance. When a resonator such as RF filter is integrated with a mixer, impedance characteristic of 50 ohm is maintained only in RF band, not in LO band resulting deterioration of flatness performance because of LO power variation on the diode. In the paper, we suggest a design method of mixer integrated with image rejection filter and LO harmonic filter to have a better performance of flatness using embedding electrical length between filter and mixer's port. Frequency specification of fabricated mixer is $21.2{\sim}22.6\;GHz$ for RF, $19.32{\sim}20.72\;GHz$ for LO and 1.88 GHz+/-50 MHz for IF, respectively. Measured results show conversion loss of 8.5 dB, flatness of 2 dB, input PldB of 8 dBm, IIP3 of 15 dBm under LO power level of 10 dBm. Return losses of RF, LO and IF port are under -12 dB, -10 dB and -5 dB, respectively. Isolations of LO/RF and LO/IF are 20 dB and 50 dB, respectively.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.18 no.4
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• pp.504-510
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• 2017

This paper presents an AC-DC power module design and evaluates its efficiency and reliability when used for electronics appliances. This power module consists of a PWM control IC, power MOSFETs, a transformer and several passive devices. The module was tested at an input voltage of 220V (RMS) (frequency 60 Hz). A test was conducted in order to evaluate the operation and power efficiency of the module, as well as the reliability of its protection functions, such as its over-current protection (OVP), overvoltage protection (OVP) and electromagnetic interference (EMI) properties. Especially, we evaluated the thermal shut-down protection (TSP) function in order to assure the operation of the module under high temperature conditions. The efficiency and reliability measurement results showed that at an output voltage of 5 V, the module had a ripple voltage of 200 mV, power efficiency of 73 % and maximum temperature of $80^{\circ}C$ and it had the ability to withstand a stimulus of high input voltage of 4.2 kV during 60 seconds.

• Korean Journal of Remote Sensing
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• v.23 no.2
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• pp.137-144
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• 2007

In KORDI (Korea Ocean Research and Development Institute), the KOSC (Korea Ocean Satellite Center) construction project is being prepared for acquisition, processing and distribution of sensor data via L-band from GOCI (Geostationary Ocean Color Imager) instrument which is loaded on COMS (Communication, Ocean and Meteorological Satellite); it will be launched in 2008. Ansan (the headquarter of KORDI) has been selected for the location of KOSC between 5 proposed sites, because it has the best condition to receive radio wave. The data acquisition system is classified into antenna and RF. Antenna is designed to be $\phi$ 9m cassegrain antenna which has 19.35 G/T$(dB/^{\circ}K)$ at 1.67GHz. RF module is divided into LNA (low noise amplifier) and down converter, those are designed to send only horizontal polarization to modem. The existing building is re-designed and arranged for the KOSC operation concept; computing room, board of electricity, data processing room, operation room. Hardware and network facilities have been designed to adapt for efficiency of each functions. The distribution system which is one of the most important systems will be constructed mainly on the internet. and it is also being considered constructing outer data distribution system as a web hosting service for offering received data to user less than an hour.