• Journal of Power Electronics
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• v.19 no.5
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• pp.1108-1121
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• 2019

The non-inverting buck-boost converter (NIBB) is a step-up and step-down DC-DC converter suitable for wide-input-voltage-range applications. However, when the input voltage is close to the output voltage, the NIBB needs to operate in the buck-boost mode, causing a significant efficiency reduction since all four switches operates in the PWM mode. Considering both the current stress limitation and the efficiency optimization, a novel design methodology for the optimal phase-shift modulation of a NIBB in the buck-boost mode is proposed in this paper. Since the four switches in the NIBB form two bridges, the shifted phase between the two bridges can serve as an extra degree of freedom for performance optimization. With general phase-shift modulation, the analytic current expressions for every duty ratio, shifted phase and input voltage are derived. Then with the two key factors in the NIBB, the converter efficiency and the switch current stress, taken into account, an objective function with constraints is derived. By optimizing the derived objective function over the full input voltage range, an offline design methodology for the optimal modulation scheme is proposed for efficiency optimization on the premise of current stress limitation. Finally, the designed optimal modulation scheme is implemented on a DSPs and the design methodology is verified with experimental results on a 300V-1.5kW NIBB prototype.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.11
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• pp.9-16
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• 2005

This paper proposes a programmable PLL (phase locked loop) based clock generator supporting a wide-range-frequency input and output for high performance and low power SoC with multiple clock frequencies domains. The propose system reduces the locking time and obtains a wide range operation frequency by using a dual-charge pumps scheme. For low power operation of a chip, the locking processing circuits of the proposed PLL doesn't be working in the standby mode but the locking data are retained by the DAC. Also, a tracking ADC is designed for the fast relocking operation after stand-by mode exit. The programmable output frequency selection's circuit are designed for supporting a optimized DFS operation according to job tasks. The proposed PLL-based clock system has a relock time range of $0.85{\mu}sec{\sim}1.3{\mu}sec$($24\~26$cycle) with 2.3V power supply, which is fabricated on $0.35{\mu}m$ CMOS Process. At power-down mode, PLL power saves more than $95\%$ of locking mode. Also, the PLL using programmable divider has a wide locking range ($81MHz\~556MHz$) for various clock domains on a multiple IPs system.

• Journal of electromagnetic engineering and science
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• v.3 no.2
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• pp.86-90
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• 2003

A flat conversion loss in microwave mixer is hard to achieve if integrating with an image rejection filter(IRF). This is due to the change of termination condition with respect to the LO and IF frequency at RF port where the filter has 50 ohm termination property only in the RF band. This paper describes a flatness maintenance in the down mixer concerning a diode matching condition as well as an electrical length of embedding line at RF port. The implemented single balance diode mixer is suitable for a 23 ㎓ European Terrestrial Radio. RF, LO and fixed IF frequency chosen in this paper are 21.2∼22.4 ㎓, 22.4∼23.6 ㎓ and 1.2 ㎓, respectively. The measured results show a conversion loss of 8.5 ㏈, flatness of 1.2 ㏈ p-p, input P1㏈ of 7㏈m, IIP3 of 15.42 ㏈m with nominal LO power level of 10㏈m. The return loss of RF and LO port are less than - 15 ㏈ and - 12 ㏈, respectively and IF port is less than - 6 ㏈. LO/RF and LO/IF isolation are 18 ㏈ and 50 ㏈, respectively. This approach would be a helpful reference for designing up/down converter possessing a filtering element.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.6 no.7
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• pp.1055-1061
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• 2002

This paper deals with a design and fabrication of an electronic ballast for 70[W] ceramic discharge metal halide lamps. The proposed ballast is composed of a rectifier, an active power factor correction circuit (PFC), a half-bridge inverter, a LC resonant circuit and a microprocessor. The developed ballast also includes a specially designed time circuit which provides reignition signal of lamps. Running frequency of the ballast is .jet at 40[kHz] to avoid acoustic-resonance and flickering. From the experimental results, input power factor and efficiency of the ballast are estimated 99.8[%] and 93.1[%], respectively.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.05a
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• pp.137-140
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• 2008

본 논문에서는 높은 주파수에서 이미지신호에 따른 하향변환기의 선현성을 우수하게 나타내기 위하여 이미지 제거 특성이 우수한 능동소자를 선택하여 VSAT 위성통신용 Ka-band 하향변환기를 설계 및 제작하였다. 하향변환기의 구성은 저잡음 증폭기단, 이미지 제거 필터, 주파수 혼합기, 주파수 체배기, 전압제어 감쇄단 및 IF단으로 구성하였고, RF 경로의 동작 유무를 판단하기 위하여 국부 루프 경로로 구성되어 있다. 하향변환기의 이득은 $11.73{\sim}13.23dB$, 잡음지수 4.4dB 이하, 50dBc 이상의 이미지 제거 특성을 나타내어, 본 논문에서 제작한 하향변환기는 고속/광 대역폭을 가지는 디지털 통신 시스템에도 적용할 수 있다.

• Proceedings of the KIEE Conference
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• 2004.07c
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• pp.2034-2036
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• 2004

In this paper, a low noise amplifier (LNA) in receiver of Low Noise Block Down Converter (LNB) for direct broadcasting service (DBS) is implemented by using GaAs HEMT. The LNA is designed for operation between 10.7GHz-12.7GHz. The LNA consists of input, output matching circuits, DC-blocks and RF-chokes. Simulation result of the LNA shows that a noise figure is less than 1.4dB and a gain is greater than 9.2dB in the bandwidth of 10.7 to 12.7GHz with good flatness of 0.1dB.

• 한국신재생에너지학회:학술대회논문집
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• 2010.11a
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• pp.171-171
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• 2010

An innovative design of a floating-buoy wave energy converter (WEC) using hydrostatic transmission (HST), named HSTWEC, is presented in this paper. The system is designed to convert ocean wave fluctuation into electricity by using the HST circuit and an electric generator. Based on the floating-buoy concept, the wave forces the sub-buoy to move up and down. Consequently, the electric power can be obtained from the generator in both the moving directions of the sub-buoy through the HST circuit as shown in Fig. 1. In order to investigate the HSTWEC operations, a mathematical model of the system is indispensible. In addition, the method to control the HSTWEC, including: pump displacement control, tension adjustment control and ballast weight control, is also discussed in this paper. Finally, the design concept as well as simulation results indicated that this HSTWEC design is an effective solution and possible to fabricate for wave energy generation.

• Proceedings of the KIEE Conference
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• 2008.04c
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• pp.215-217
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• 2008

This paper describes development of hardware simulator for the PMSG wind power system, which was designed considering wind characteristic, blade characteristic and blade inertia compensation. The simulator generates torque and speed signals for a specific wind turbine with respect to given wind speed. This torque and speed signals are scaled down to fit the input of 2kW PMSG. The PMSG-side converter operates to track the maximum power point, and the grid-side inverter controls the active and reactive power supplied to the grid. The operational feasibility was verified by computer simulations with PSCAD/EMTDC, and the implementation feasibility was confirmed through experimental works with a hardware set-up.

• Proceedings of the IEEK Conference
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• 2001.09a
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• pp.951-954
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• 2001

본 논문에서는 SDR (Software Defined Radio)시스템을 위한 디지털 IF (Intermediate Frequency)수신기를 구현하였다[1][2]. 구현된 수신기의 하드웨어 구조는 AD변환부, PDC(Programmable Down Converter)부, DSP (Digital Signal Processing)부분으로 이루어졌다. AD변환부는 Analog Devices사의 AD6644를 이용하여 아날로그 신호를14bit의 디지털 신호로 변환된다. PDC부분은 Intersil사의 HSP 50214B를 이용하여 14bit 샘플 된 IF(Intermediate Frequency)입력을 혼합기와 NCO(Numerically Controlled Oscillator)에 의해 기저대역으로 다운 시키는 역할을 한다. PDC는 CIC (Cascaded Integrator Comb)필터, Halfband 필터 그리고 프로그램할 수 있는 FIR필터로 구성되어 있다. 그리고 PDC부분을 제어하고 PDC부분에서 처리할 수 없는 캐리어, 심볼 트래킹을 위해 Texas Instrument사의 16비트의 고정소수점 DSP인 TMS320C5416과 Altera사의 FPGA를 사용하였다. 그러므로 중간주파수 대역과 기저대역 간의 신호변환을 디지털 신호처리를 수행함으로써 일반적인 아날로그 처리방식보다 고도의 유연성과 고성능 동작이 가능하고 시간과 환경 변화에 우수한 동작 특성을 제공한다.

• Proceedings of the KIPE Conference
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• 2001.10a
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• pp.189-192
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• 2001

This paper proposed that an AC-DC converter system using multiple buck-chopper operates with four choppers connecting to a number of parallel circuits. To improve these, a large number of soft switching topologies included a resonant circuit have been proposed. And, some simulative results on computer are included to confirm the validity of the analytical results. The partial resonant circuit makes use of an inductor using step-down and a condenser of loss-less snubber. The result is that the switching loss is very low and the efficiency of system is high. And the snubber condenser used in a partial resonant circuit makes charging energy regenerated at input power source for resonant operation. The proposed conversion system is deemed the most suitable for high power applications where the power switching devices are used.