• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.9
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• pp.182-189
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• 2014

A tapped delay line time-to-digital converter (TDC) can be easily implemented using internal carry chains in a field-programmable gate array, and hence, its use is widespread. However, the tapped delay line TDC suffers from performance degradation because of differences in the delay times of dedicated carry chains. In this paper, a dual edge measurement method is proposed instead of a typical step signal to the delay cell to compensate for the performance degradation caused by wide-delay cells in carry chains. By applying a pulse of a fixed width as an input to the carry chains and using the time information between the up and down edges of the signal pulse, the timing accuracy can be increased. Two dedicated carry chain sites are required for the dual edge measurements. By adopting the proposed dual edge measurement method, the average delay widths of the two carry chains were improved by more than 35%, from 17.3 ps and 16.7 ps to 11.2 ps and 10.1 ps, respectively. In addition, the maximum delay times were improved from 41.4 ps and 42.1 ps to 20.1 ps and 20.8 ps, respectively.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.11A
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• pp.933-940
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• 2011

In this paper, Ka-band transceiver for road watch radar system is designed and fabricated. The transceiver for road watch radar system is composed of waveform generator, frequency generator. IF transceiver and RF up/down converter. The transceiver especially has 3 different waveform mode for target detection range. The transceiver had over 150 MHz bandwidth in Ka-band and 22 dBm output power. The receiver gain and noise figure was 30 dB and 4 dB respectively. The receive dynamic range was 65.28dB and amplitude imbalance and phase imbalance of I/Q channel was 0.3 dB and 1.8 degree respectively. The transceiver meets the required electrical performances through the individual tests.

• ETRI Journal
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• v.32 no.2
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• pp.214-221
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• 2010

Radio frequency (RF) subsampling can be used by radio receivers to directly down-convert and digitize RF signals. A goal of a cognitive radio/software defined ratio (CR/SDR) receiver design is to place the analog-to-digital converter (ADC) as near the antenna as possible. Based on this, a band-pass sampling (BPS) frontend for CR/SDR is proposed and verified. We present a receiver architecture based second-order BPS and signal processing techniques for a digital RF frontend. This paper is focused on the benefits of the second-order BPS architecture in spectrum sensing over a wide frequency band range and in multiband receiving without modification of the RF hardware. Methods to manipulate the spectra are described, and reconstruction filter designs are provided. On the basis of this concept, second-order BPS frontends for CR/SDR systems are designed and verified using a hardware platform.

• Journal of Digital Convergence
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• v.10 no.10
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• pp.313-318
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• 2012

In this study, we propose a low-noise transceiver for 10GHz motion sensor. The transceiver presented here has a circuit(Hittite HMC908LC5) that is composed of a two way-$0^{\circ}$ power splitter(the 1:2 block) and a $90^{\circ}$ Hybrid. The noise reduction circuit utilizes an LNA followed by an image reject mixer which is driven by an LO buffer amplifier. A modeling and analysis have been pursued using CST MWS. A prototype sensor was manufactured to measure the performance and experimental results show that the proposed sensor is good enough to use for a accurate motion sensor.

• Journal of electromagnetic engineering and science
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• v.5 no.1
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• pp.8-13
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• 2005

The InGaP/GaAs hetero-junction bipolar transistor(HBT) monolithic voltage-controlled dielectric resonator oscillator(VCDRO) is first demonstrated for a Ku-band low noise block down-converter(LNB) system. The on-chip voltage control oscillator core employing base-collector(B-C) junction diodes is proposed for simpler frequency tuning and easy fabrication instead of the general off-chip varactor diodes. The fabricated VCDRO achieves a high output power of 6.45 to 5.31 dBm and a wide frequency tuning range of ]65 MHz( 1.53 $\%$) with a low phase noise of below -95dBc/Hz at 100 kHz offset and -115 dBc/Hz at ] MHz offset. A]so, the InGaP/GaAs HBT monolithic DRO with the same topology as the proposed VCDRO is fabricated to verify that the intrinsic low l/f noise of the HBT and the high Q of the DR contribute to the low phase noise performance. The fabricated DRO exhibits an output power of 1.33 dBm, and an extremely low phase noise of -109 dBc/Hz at 100 kHz and -131 dBc/Hz at ] MHz offset from the 10.75 GHz oscillation frequency.

• The Journal of the Korea institute of electronic communication sciences
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• v.13 no.3
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• pp.503-508
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• 2018

This study describes the design and implementation of EGSE for Digital Satellite Communication. The EGSE is a equipment that evaluates digital satellite communication and requires precise and accurate measurement. EGSE consists of a PLDIU and IIU(Instrument Interface Unit), Up/Down converter for SHF band, Modems to verify the Digital Satellite Communication. The EGSE was used for performance verification and space environment test such as thermal vacuum after developing digital satellite communication.

• Proceedings of the KIPE Conference
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• 2000.07a
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• pp.493-497
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• 2000

A battery is the device that transforms the chemical energy into the direct-current electrical energy without a mechanical process. Unit cells are connected in series to obtain the required voltage while being connected in parallel to organize capacity for load current. Because the voltage drop down in one set of battery is faster than in two one it may result in the low efficiency of power converter with the voltage drop and cause the system shutdown. However when the system being shutdown. However when the system being driven in parallel a circular-current can be generated,. It is shown that as a result the new batteries are heated by over-charge and over-discharge and the over charge current increases rust of the positive grid and consequently shortens the lifetime of the new batteries. The difference between the new batteries and old ones is the amount of internal resistance. In this paper we can detect the unbalance current using the microprocessor and achieve the balance current by adjusting resistance of each set, The internal resistance of each set becomes constant and the current of charge and discharge comes to be balanced by inserting the external resistance into the system and calculating the change of internal resistance.

• Proceedings of the KIEE Conference
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• 2009.07a
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• pp.932_933
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• 2009

A technology based on thyristors will be used to manufacture the super-conducting coil AC/DC converters because of the low ratio of cost over installed power compared to a design based on GTO or similar technology. But phase-controlled converter suffers from fundamental disadvantage. They inject current harmonics into the input ac mains due to their nonlinear characteristics, thereby distort the supply voltage waveform, and demand reactive power from the associated ac power system at retarded angles. To overcome this disadvantage, in the case of two series converters at the DC side, connected to the same step-down transformer, apply for the sequence control. It is the most simple and efficient way to reduce the reactive power consumption at low cost. Analytical sequence control algorithm is suggested, the validity of the proposed scheme has been verified by experimental results with the small-scaled International Thermonuclear Experimental Reactor (ITER) Power Supply to minimize reactive power consumption.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.6 no.2
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• pp.151-158
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• 2002

In this paper, Phase locked microwave oscillator having the low phase noise and high stability for digital MMDS down converter was designed. we have been analyzed the low phase noise properties by the active device nonlinear equivalent circuits and derived the necessary and sufficient conditions for high stable voltage control oscillator. And it is applied to phase locked loop, we design the phase locked microwave oscillator of frequency synthesizer. Experimental results of designed phase locked oscillator shows -85dBc/Hz @ 10KHz phase noise properties and simulation result is -90Bc/Hz @ 10kHz respectively we shows that proposed low phase noise and stable conditions of phase locked microwave oscillator can be applied to design the high stable digital MMDS frequency synthesizer.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.2 no.2 s.3
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• pp.97-101
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• 2003

A MMIC (monolithic microwave integrated circuit) mixer chip using the Schottky diode of an InGahs/CaAs p-HEMT process has been developed for the receiver down converter of Ku-band. A different approach to the MMIC mixer structure is applied for reducing the chip size by the exchange of ports between If and LO. This MMIC covers with RF (14.0 - 14.5 GHz) and If (12.252 - 12.752 GHz). According to the on-wafer measurement, the miniature (3.3X3.0 m) MMIC mixer demonstrates conversion loss below 9.8 dB, RF-to-IF isolation above 23 dB, LO-to-IF isolation above 38 dB, respectively.