• Title/Summary/Keyword: Down converter

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Two-phase Double Step-down DC-DC Converter Using Coupled Inductor (결합 인덕터를 이용한 2상 이중 강압형 직류-직류 컨버터)

  • Jeong, Seongyong;Cha, Honnyong;Kim, Heung-Geun
    • Proceedings of the KIPE Conference
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    • 2014.07a
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    • pp.159-160
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    • 2014
  • 기존 인터리브드 방식의 2상 이중 강압형 직류-직류 컨버터는 비절연 강압형 직류-직류 컨버터로 출력 전류 리플 감소, 이중 강압으로 인한 스위치 전압 스트레스 감소, 인덕터 전류 불평형 문제 해결, 그리고 스위칭 손실 감소 등의 장점으로 대용량 직류-직류 컨버터에 적합하다. 본 논문에서는 기존의 2상 이중 강압형 직류-직류 컨버터에 결합 인덕터를 적용하여 인덕터의 전류 리플을 감소시키고 이를 수치적으로 해석한다. 또한 결합 인덕터의 문제점인 각 상의 인덕터 전류 불평형으로 인한 인덕터 포화현상에 대하여 실험을 통해 확인 한다.

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Development of hardware simulator for PMSG wind power system composed of anemometer and motor-generator set (풍속계와 Motor-Generator를 이용한 영구자석동기발전기 풍력발전시스템 하드웨어 시뮬레이터 개발)

  • Jeong, Jong-Kyou;Han, Byung-Moon
    • Proceedings of the KIPE Conference
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    • 2010.11a
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    • pp.248-249
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    • 2010
  • This paper describes development of hardware simulator for the PMSG(Permanent Magnet Synchronous Generator) wind power system, which was designed using real wind data. The simulator consists of a realistic wind turbine model using anemometer, vector drive, induction motor. The turbine simulator generates torque and speed signals for a specific wind turbine with respect to given wind speed. This torque and speed signals are scaled down to fit the input of 3kW PMSG. The PMSG-side converter operates to track the maximum power point and the grid-side inverter controls the active and reactive power supplied to the grid. The operational feasibility was first verified by computer simulations with PSCAD/EMTDC. The feasibility of real system implementation was confirmed through experimental works with a hardware set-up.

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Load and Capacitor Stacking Topologies for DC-DC Step Down Conversion

  • Mace, Jules;Noh, Gwangyol;Jeon, Yongjin;Ha, Jung-Ik
    • Journal of Power Electronics
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    • v.19 no.6
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    • pp.1449-1457
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    • 2019
  • This paper presents two voltage domain stacking topologies for powering integrated digital loads such as multiprocessors or 3D integrated circuits. Pairs of loads and capacitors are connected in series to form a stack of voltage domains. The voltage is balanced by switching the position of the capacitors in one case and the position of the loads in the other case. This method makes the voltage regulation robust to large differential load power consumption. The first configuration can be named the load stacking topology. The second configuration can be named the capacitor stacking topology. This paper aims at proposing and comparing these two topologies. Models of both topologies and a switching scheme are presented. The behavior, control scheme, losses and overall performance are analyzed and compared theoretically in simulation and experiments. Experimental results show that the capacitor stacking topology has better performance with a 30% voltage ripple reduction.

Design of a CCM/DCM dual mode DC-DC Buck Converter with Capacitor Multiplier (커패시터 멀티플라이어를 갖는 CCM/DCM 이중모드 DC-DC 벅 컨버터의 설계)

  • Choi, Jin-Woong;Song, Han-Jung
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.17 no.9
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    • pp.21-26
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    • 2016
  • This paper presents a step-down DC-DC buck converter with a CCM/DCM dual-mode function for the internal power stage of portable electronic device. The proposed converter that is operated with a high frequency of 1 MHz consists of a power stage and a control block. The power stage has a power MOS transistor, inductor, capacitor, and feedback resistors for the control loop. The control part has a pulse width modulation (PWM) block, error amplifier, ramp generator, and oscillator. In this paper, an external capacitor for compensation has been replaced with a multiplier equivalent CMOS circuit for area reduction of integrated circuits. In addition, the circuit includes protection block, such as over voltage protection (OVP), under voltage lock out (UVLO), and thermal shutdown (TSD) block. The proposed circuit was designed and verified using a $0.18{\mu}m$ CMOS process parameter by Cadence Spectra circuit design program. The SPICE simulation results showed a peak efficiency of 94.8 %, a ripple voltage of 3.29 mV ripple, and a 1.8 V output voltage with supply voltages ranging from 2.7 to 3.3 V.

Design of Power IC Driver for AMOLED (AMOLED 용 Power IC Driver 설계)

  • Ra, Yoo-Chan
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.19 no.5
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    • pp.587-592
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    • 2018
  • Because the brightness of an AMOLED is determined by the flowing current, each pixel of AMOLED operates via A current driving method. Therefore, it is necessary to supply power to adjust the amount of current according to THE user's requirement for AMOLED driving. In this study, an IP driver block was designed and a simulation was conducted for an AMOLED display, which supplies power as selected by users. The IP driver design focused on regulating the output power due to the OLED characteristics for the diode electric current according to the voltage to be activated by pulse-skipping mode (PSM) under low loads, and 1.5 MHz pulse-width modulation (PWM) for medium/high loads. The IP driver was designed to eliminate the ringing effects appearing from the dis-continue mode (DCM) of the step-up converter. The ringing effects destroy the power switch within the IC, or increase the EMI to the surrounding elements. The IP driver design minimized this through a ringing killer circuit. Mobile applications were considered to enable true shut-down capability by designing the standby current to fall below $1{\mu}A$ to disable it. The driver proposed in this paper can be applied effectively to the same system as the AMOLED display dual power management circuit.

Design of 77 GHz Automotive Radar System (77 GHz 차량용 레이더 시스템 설계)

  • Nam, Hyeong-Ki;Kang, Hyun-Sang;Song, Ui-Jong;Cui, Chenglin;Kim, Seong-Kyun;Nam, Sang-Wook;Kim, Byung-Sung
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.24 no.9
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    • pp.936-943
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    • 2013
  • This work presents the design and measured results of the single channel automotive radar system for 76.5~77 GHz long range FMCW radar applications. The transmitter uses a commercial GaAs monolithic microwave integrated circuit(MMIC) and the receiver uses the down converter designed using 65 nm CMOS process. The output power of the transmitter is 10 dBm. The down converter chip can operate at low LO power as -8 dBm which is easily supplied from the transmitter output using a coupled line coupler. All MMICs are mounted on an aluminum jig which embeds the WR-10 waveguide. A microstrip to waveguide transition is designed to feed the embedded waveguide and finally high gain horn antennas. The overall size of the fabricated radar system is $80mm{\times}61mm{\times}21mm$. The radar system achieved an output power of 10 dBm, phase noise of -94 dBc/Hz at 1 MHz offset and a conversion gain of 12 dB.

Design of 8bit current steering DAC for stimulating neuron signal (뉴런 신호 자극을 위한 8비트 전류 구동형 DAC)

  • Park, J.H.;Shi, D.;Yoon, K.S.
    • Journal of rehabilitation welfare engineering & assistive technology
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    • v.7 no.2
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    • pp.13-18
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    • 2013
  • In this paper design a 8 bit Current Steering D/A Converter for stimulating neuron signal. Proposed circuit in paper shows the conversion rate of 10KS/s and the power supply of 3.3V with 0.35um Magna chip CMOS process using full custom layout design. It employes segmented structure which consists of 3bit thermometer decoders and 5bit binary decoder for decreasing glitch noise and increasing resolution. So glitch energy is down by $10nV{\bullet}sec$ rather than binary weighted type DAC. And it makes use of low power current stimulator because of low LSB current. And it can make biphasic signal by connecting with Micro Controller Unit which controls period and amplitude of signal. As result of measurement INL is +0.56/-0.38 LSB and DNL is +0.3/-0.4 LSB. It shows great linearity. Power dissipation is 6mW.

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Study on The Technical Improvement in Wireless Power Communication System with Low Power (무선전력통신 시스템의 저전력화를 위한 기술적 개선방안)

  • Chung, Sung-In;Lee, Seung-Min;Lee, Hyo-Sung;Lee, Hug-Ho
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.47 no.1
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    • pp.53-57
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    • 2010
  • This study proposes the algorithm which drives the powerless without battery. The exiting wire or RF type dosimeter, which is the computation of the real time with battery on the dose radiation exposure, In the Wired dosimeter, it is trouble to need the maintenance and management by periods. Besides, the case of the RF typed dosimeter with battery, it is requested to size bigger and to replace battery frequently and so on. Especially RF typed dosimeter has trouble to need for the embody with large power consumption on the contactless typed dosimeter. As the method for the low power, the study designed to be down the operating clock of the MPC, to improve the efficiency of the rectifier, to eliminate the external memory and the DC-DC converter for the simplification of the circuit We convince our research contributes not only to understand the simplified circuit and miniaturization, but also to help the design and application technology of the powerless dosimeter.

A Web Services Delivery System for Mobile Environment (모바일 환경을 위한 웹 서비스 전송 시스템)

  • Kim, Jin-Il;Kim, Yong-Tae;Park, Gil-Cheol
    • Journal of the Korea Society of Computer and Information
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    • v.13 no.6
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    • pp.203-210
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    • 2008
  • Recently, as wireless communication are becoming more and more popular, Internet users is becoming increasingly demand HTTP-based web service in mobile computing environment. But, overall performance of web services may slow down, because mobile device are generally equipped with lower capability. Therefore, the most important factor to design wireless internet delivery system should be scalable to handle a large scale traffic due to rapidly growing users. But, in case of some preceding research, they not present a basic efficiency reform measure until currently. Therefore, In this paper, We propose a Web Service Delivery System for mobile environment that alleviates problems that occurred while executing web services in mobile environment and are helpful to overcome the above needs. The system composed of HTML/WML Converter, SOAP message processor. We compare the existing system with the proposed system.

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Design of Wideband Ku-band Low Noise Down-converter for Satellite Broadcasting (Ku-band 광대역 위성방송용 LNB 설계)

  • Hong, Do-Hyeong;Mok, Gwang-Yun;Park, Gi-Won;Rhee, Young-Chul
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2015.10a
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    • pp.941-944
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    • 2015
  • In this paper study for VSAT(very small aperture terminal) LNB(low noise block). ship LNB was demanded high stability and low noise figure. We designed FEM(Front-End Module) that was operated multi-band. FEM designed was constructed in a multi-band low noise receiver amplifier, a frequency converter, IF amplifier, Voltage Control Oscillator signal generating circuit four circuit using. To convert the multi-band 2.05GHz band, it generates four local oscillator signals, the four(band1, band2, band3, band4) designed to output an IF signal developed conversion apparatus, the conversion gain 64dB, noise figure 1dB or less, output P1dB 15dBm or more, phase noise showed -73dBc@100Hz.

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