• Title/Summary/Keyword: Down converter

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The Experimental Study about Kinetic Change of Water Surface in the Chambers for Wave Energy Converter (파력발전용 수조실의 수면 운동 변화에 대한 실험적 연구)

  • Hadano, Kesayoshi;Moon, Byung-Young;Lee, Seong-Beom;Kim, Kwang-Jung
    • The KSFM Journal of Fluid Machinery
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    • v.17 no.2
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    • pp.41-47
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    • 2014
  • Experimental results are given for the vertical motion of water in the water chambers for wave energy converter aligned along the wave propagation direction in order to avoid the impulsive wave forces. This paper mainly focuses on the property of the amplitude of the vertical motion of the water surface in the chambers. The amplification has been investigated by dimensionless parameters of wave period to resonance period ratio of the U-shaped oscillation, $T/T_r$, chamber size to wave length ratio, l/L, water depth to wave length ratio, h/L, amplitude of up-down motion of water particles to draft of the front wall ratio, ${\zeta}/D$. It has been shown that l/L should be less than 0.1 and as $T/T_r$ approaches unity the up-down of the water in the chambers is amplified. Also, the structure of the walls which form th water chambers has been examined roughly. It is deduced that the chambers set on both sides of the hull of a single-point moored floating vessel is preferable to those set along a fixed structure such as breakwaters.

The Fast Correlative Vector Direction Finder Conversion (직접 변환을 이용한 고속 상관형 벡터 방향탐지기)

  • Park, Cheol-Sun;Kim, Dae-Young
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.43 no.12 s.354
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    • pp.16-23
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    • 2006
  • This paper presents the development of the fast Direction Finder using direct conversion method, which can intercept for short pulse signal of less' than 1 msec. in RF Down Converter, and CVDF(Correlative Vector Direction Finding) algorithm, which estimates DoA (Direction of Arrival). The configuration and characteristics of direction finder using 5-channel equi-spaced circular array antenna are presented and the direct conversion techniques for removing tuning time using I/Q demodulator are described. The CRLB of our model is derived, the principles of 2 kind of CVDF algorithm are explained and their characteristics are compared with CRLB w.r.t the number of samples and spacing ratio. The RF Down Converter prototype using direct conversion method is manufactured, the 2 kind of CVDF algorithm are applied and their performance are analyzed. Finally it is confirmed the LSE based CVDF algorithm is better than correlation-coefficient based except for ambiguity protection capabilities.

Implementation of Ka-band Satellite Broadcasting/LNB with High Dynamic Range (Ka-band 고감도 위성방송용/LNB 최적화 설계)

  • Mok, Gwang-Yun;Lee, Kyung-Bo;Rhee, Young-Chul
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2016.10a
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    • pp.66-69
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    • 2016
  • In this paper, we suggests a Ka-band LNB considering next-generation UHD satellite TVRO. Since Ka-band has grater attenuation than Ku-band in atmosphere, we designed the low-noise down-converter to improve receiving sensitivity and to extend a dynamic range of receiver. It aims to compensate a quality of ultra high definition transmission signal for rainfall. The low-noise block diagram consists of a three-staged amplifier (LNA), band-pass filter for deleting image (BPF), mixer and IF when considering nonlinear characteristics in the receiver RF front end module. Also, we showed a LNB through optimization processes affecting dynamic range directly in receiver FEM. Asa resuly of experiment, the gain of low-noise down-converter show between 58.5dB and 60.7dB, the noise figure has a high characteristic as 1.38dB. Finally, the phase noise of local oscillator is -63.10dBc at 100MHz offset frequency.

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Simulation of Micro-SMES System using PSCAO/EMTOC (PSCAD/EMTDC를 이용한 Micro-SMES의 시뮬레이션)

  • Kim, Bong-Tae;Park, Min-Won;Seong, Ki-Chul;Yu, In-Keun
    • Proceedings of the KIEE Conference
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    • 2002.07b
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    • pp.1361-1363
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    • 2002
  • Micro-SMES(Superconducting Magnetic Energy Storage) has been studied as an impulsive high power supply for industrial applications. Recently, electric power reliability of our country has been improved. However, there are still remaining problems which are short-duration variations like instantaneous and momentary interruption and voltage sag by nature calamity ; typhoon, lightning, snow, etc. Besides, power quality ; harmonics, goes down because of using power electronics equipments. Malfunction of controller and stop machinery, and losing important data are caused by poor power quality at a couple of second in accuracy controllers. Due to those, battery based UPS has been used, but there are several disadvantages ; long charge and discharge time, environmental problem by acid and heavy metal, and short life time. Micro-SMES is an alternative to settle problems mentioned above. However, there need huge system apparatuses in order to verify the effect of system efficiency and stability considering the size of micro-SMES, the sort of converter type, and various conditions. This paper presents a cost effective simulation method of micro-SMES and power converter, and design for micro-SMES based system using PSCAD/EMTDC.

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A los voltage high speed 8 bit CMOS digital-to-analog converter with two-stage current cell matrix architecture (2단 전류셀 매트릭스 구조를 지닌 저전압 고속 8비트 CMOS D/A 변환기)

  • 김지현;권용복;윤광섭
    • Journal of the Korean Institute of Telematics and Electronics C
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    • v.35C no.4
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    • pp.50-59
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    • 1998
  • This paper describes a 3.3V 8bit CMOS digital to analog converter (DAC) with two state current cell metrix architecture which consists of a 4 MSB and a 4 LSB current matrix stage. The symmetric two stage current cell matrix architecture allow the designed DAC to reduce hot only a complexity of decoding logics, but also a number of wider swing cascode curent mirros. The designed DAC with an active chip area of 0.8 mm$_{2}$ is fabricated by a 0.8 .mu.m CMOS n-well standard digital process. The experimental data shows that the rise/fall time, the settling time, and INL/DNL are6ns, 15ns, and a less than .+-.0.8/.+-.0.75 LB, respectively. The designed DAC is fully operational for the power supply down to 2.0V, such that the DAC is suitable for a low voltage and a low power system application. The power dissipation of the DAC with a single power supply of 3.3V is measured to be 34.5mW.

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A Cascaded D-STATCOM Integrated with a Distribution Transformer for Medium-voltage Reactive Power Compensation

  • Lei, Ertao;Yin, Xianggen;Chen, Yu;Lai, Jinmu
    • Journal of Power Electronics
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    • v.17 no.2
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    • pp.522-532
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    • 2017
  • This paper presents a novel integrated structure for a cascaded distribution static compensator (D-STATCOM) and distribution transformer for medium-voltage reactive power compensation. The cascaded multilevel converter is connected to a system via a group of special designed taps on the primary windings of the Dyn11 connection distribution transformer. The three-phase winding taps are symmetrically arranged and the connection point voltage can be decreased to half of the line-to-line voltage at most. Thus, the voltage stress for the D-STATCOM is reduced and a compromise between the voltage rating and the current rating can be achieved. The spare capacity of the distribution transformer can also be fully used. The working mechanism is explained in detail and a modified control strategy is proposed for reactive power compensation. Finally, both simulation and scaled-down prototype experimental results are provided to verify the feasibility and effectiveness of the proposed connection structure and control strategy.

A 3.1 to 5 GHz CMOS Transceiver for DS-UWB Systems

  • Park, Bong-Hyuk;Lee, Kyung-Ai;Hong, Song-Cheol;Choi, Sang-Sung
    • ETRI Journal
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    • v.29 no.4
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    • pp.421-429
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    • 2007
  • This paper presents a direct-conversion CMOS transceiver for fully digital DS-UWB systems. The transceiver includes all of the radio building blocks, such as a T/R switch, a low noise amplifier, an I/Q demodulator, a low pass filter, a variable gain amplifier as a receiver, the same receiver blocks as a transmitter including a phase-locked loop (PLL), and a voltage controlled oscillator (VCO). A single-ended-to-differential converter is implemented in the down-conversion mixer and a differential-to-single-ended converter is implemented in the driver amplifier stage. The chip is fabricated on a 9.0 $mm^2$ die using standard 0.18 ${\mu}m$ CMOS technology and a 64-pin MicroLead Frame package. Experimental results show the total current consumption is 143 mA including the PLL and VCO. The chip has a 3.5 dB receiver gain flatness at the 660 MHz bandwidth. These results indicate that the architecture and circuits are adaptable to the implementation of a wideband, low-power, and high-speed wireless personal area network.

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RF Transceiver Design and Implementation for Common Data Link (공용 데이터링크 RF 송수신기 설계 및 구현)

  • Kim, Joo-Yeon
    • Journal of IKEEE
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    • v.19 no.3
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    • pp.371-377
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    • 2015
  • This paper is about the RF transceiver designed and implementation for common data link. The trasmitter is configured as a frequency up-converter, a power amplifier and a duplexer. The receiver is configured as a duplxer, a frequency down-converter and a low noise amplifier. The maximum transmission distance, the reception sensitivity is designed to meet the electrical and temperature characteristics and the like. Using a modeling and simulation in order to meet the requirements of the RF transceiver has been designed and implemented. Transmitting output power and Noise Figure has been measured with 38.58dBm and 5.5dB, respectively. All of the electrical and temperature specifications was meet. Was confirmed all of the requirement specification by electrical characteristics test and temperature characteristics test.

Direction for Development of Energy Regeneration Device for DC Electric Railway System (DC전철구간의 에너지회생장치 개발 방향)

  • Kim, Yong-Ki;Bae, Chang-Han;Han, Moon-Seob;Yang, Young-Chul;Jang, Su-Jin
    • Proceedings of the KSR Conference
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    • 2007.05a
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    • pp.804-808
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    • 2007
  • when electric traction system used DC 1500V runs on decline of rail road track and slows down, Dc voltage goes beyond regular voltage. In this case extra power is forcibly wasted by resister because rectifier of substation and electric train including power converter and so on are out of order. This paper described a DC electric railway system, which can generate the excessive DC power form DC bus line to AC source in substation for traction system. The proposed regeneration inverter system for DC traction can be used as both an inverter and an active power filter(APF). As a regeneration inverter mode, it can recycle regenerative energy caused by decelerating tractions and as an active power filter mode, it can compensate for harmonic distortion produced by the rectifier substation. In addition, electric traction system products harmonic current and voltage distortion and reactive power because power converter is used so regeneration inverter normally runs such as active power filter(APF) for improving power quality. From the viewpoint of both power capacity and switching losses, the system is designed on the basis of three phase PWM inverters and composed of parallel inverters, output transformers, and an LCL filter.

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All Optical Wavelength Converter for Ultra High-Speed RZ Pattern Data (RZ형 초고속 데이터에 대한 전광파장변환기)

  • Yi, Seung- Woo;Lee, Hyuk-Su;Yoon, Kyeong-Mo;Lee, Yong-Gi;Eom, Jin-Seob
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.27 no.8B
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    • pp.826-833
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    • 2002
  • Generally, it is announced that RZ pattern gives a better transmission performance than NRZ pattern in ultra-high speed transmission above 10Gbps. In this paper, we propose a wavelength converter for RZ data which can controls XPM in SOA by locating polarization controllers within optical fiber loop mirror and demonstrate its performance through simulation and 10Gbps data experiment. The proposed structure needs only one polarization dependent SOA for implementation compared to previous XPM ones to make the cost down. And it provides non-inverted pattern outputs at two output ports respectively.