• Title/Summary/Keyword: Double-base Log Encoder

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Algorithm and Design of Double-base Log Encoder for Flash A/D Converters

  • Son, Nguyen-Minh;Kim, In-Soo;Choi, Jae-Ha;Kim, Jong-Soo
    • Journal of the Institute of Convergence Signal Processing
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    • v.10 no.4
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    • pp.289-293
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    • 2009
  • This study proposes a novel double-base log encoder (DBLE) for flash Analog-to-Digital converters (ADCs). Analog inputs of flash ADCs are represented in logarithmic number systems with bases of 2 and 3 at the outputs of DBLE. A look up table stores the sets of exponents of base 2 and 3 values. This algorithm improves the performance of a DSP (Digital Signal Processor) system that takes outputs of a flash ADC, since the double-base log number representation does multiplication operation easily within negligible error range in ADC. We have designed and implemented 6 bits DBLE implemented with ROM (Read-Only Memory) architecture in a $0.18\;{\mu}m$ CMOS technology. The power consumption and speed of DBLE are better than the FAT tree and binary ROM encoders at the cost of more chip area. The DBLE can be implemented into SoC architecture with DSP to improve the processing speed.

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Design of a nonlinear ADC encoder to reduce the conversion errors in DBNS (DBNS 변환오차를 고려한 비선형 ADC 엔코더 설계)

  • Woo, Kyung-Haeng;Choi, Won-Ho;Kim, Jong-Soo;Choi, Jae-Ha
    • Journal of the Institute of Convergence Signal Processing
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    • v.14 no.4
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    • pp.249-254
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    • 2013
  • A fast multiplier and ADC are essential to process the analog signals in real time. The double-base number system(DBNS) is known as an efficient method for this purpose. The DBNS uses the numbers 2 and 3 as the base numbers simultaneously. The system has an advantage of fast multiplication, less chip area, and low power consumption compared to the binary multiplier. However, the inherent errors of the log number's intrinsic tolerance in DBNS are accumulated in a FIR digital filter, so the signal-to-noise ratio(SNR) has a tendency to be degraded. In this paper, the nonlinear encoder of ADC is designed to compensate the accumulated errors of DBNS by analysing the error distributions of various filter coefficients. The new ADC does not sacrifice its own advantages because the encoder circuits are modified only. The experiments were done with an FIR filters those were designed to have -70dB of SNR in stop band. The proposed nonlinear ADC encoder could drop the SNR to -45dB in stop band, in contrast to -35dB with the linear encoder.