• 전기학회논문지
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• 제61권3호
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• pp.373-379
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• 2012

This paper presents a fault location algorithm based on the adaptively estimated value of the local sequence source impedance for faults on a parallel transmission line. This algorithm uses only the local voltage and current signals of a faulted circuit. The remote current signals and the zero-sequence current of the healthy adjacent circuit are calculated by using the current distribution factors together with the local terminal currents of the faulted circuit. The current distribution factors consist of local equivalent source impedance and the others such as fault distance, line impedance and remote equivalent source impedance. It means that the values of the current distribution factors can change according to the operation condition of a power system. Consequently, the accuracy of the fault location algorithm is affected by the two values of equivalent source impedances, one is local source impedance and the other is remote source impedance. Nevertheless, only the local equivalent impedance can be estimated in this paper. A series of test results using EMTP simulation data show the effectiveness of the proposed algorithm. The proposed algorithm is valid for a double-circuit transmission line system where the equivalent source impedance changes continuously.

• Journal of electromagnetic engineering and science
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• 제14권1호
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• pp.36-42
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• 2014

In this paper, an epsilon near zero (ENZ) tunneling circuit using a double-ridge rectangular waveguide (RWG) is proposed for the miniaturization of a waveguide component. The proposed ENZ channel and is located in the middle of the input-output RWG (IORWG). The ratio of the height to the width of the channel waveguide is very small compared to the IORWG. By properly adjusting the ridge dimensions, the tunneling frequency of the proposed ENZ channel can be lowered to near the cut-off frequency of the IORWG. For the proposed ENZ tunneling circuit, the approach adopted for extracting the effective permittivity, effective permeability;normalized effective wave impedance, and propagation constant from the simulated scattering parameters was explained. The extracted parameters verified that the proposed channel is an ENZ channel and electromagnetic energy is tunneling through the channel. Simulation and measurement results of the fabricated ENZ channel structure agreed.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2003년도 추계학술대회 논문집 전기물성,응용부문
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• pp.151-159
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• 2003

According to the records, approximately 50 percent of power failure were caused by lightning. Conventional fault preventive measures against lightning include reduction of the footing resistance of the tower, multiplication of overhead ground wires and unbalanced insulation of the double circuit transmission tower. In addition to these, transmission line arresters have been recently appeared as an alternatives. In this paper an unbalanced insulation method with transmission line arrester was assumed as another countermeasure against simultaneous double circuit trip of 154 kV transmission line by lightning strike. The lightning performance of line arrester was compared with conventional insulation concept using different numbers of porcelain and glass insulator. Larger numbers of insulator simply increase flashover current level by lightning but the lightning performance doesn't proportional to it. EMTP simulation and predictive calculation of lightning failure rate were carried out to evaluate the performance.

• Journal of Magnetics
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• 제21권1호
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• pp.65-71
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• 2016

To increase the retaining force, a novel design for a concentric, bi-directional, electromagnetic valve actuator that contains double-layer permanent magnets is presented in this paper. To analyze the retaining-force change caused by the magnets, an equivalent magnetic circuit (EMC) model is established, while the EMC circuit of a double-layer permanent-magnet valve actuator (DLMVA) is also designed. Based on a 3D finite element method (FEM), the calculation model is built for the optimization of the key DLMVA parameters, and the valve-actuator optimization results are adopted for the improvement of the DLMVA design. A prototype actuator is manufactured, and the corresponding test results show that the actuator satisfies the requirements of a high retaining force under a volume limitation; furthermore, the design of the permanent magnets in the DLMVA allow for the attainment of both a high initial output force and a retaining force of more than 100 N.

• 한국전자파학회논문지
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• 제28권11호
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• pp.924-927
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• 2017

본 논문에서는 6~18 GHz 대역 8-비트 true time delay(TTD) 회로의 설계 및 측정결과에 대하여 기술하였다. 단위 지연 회로는 상대적으로 시간 지연 변화율이 일정한 m-유도 필터(m-derived filter)를 이용하였다. 설계한 8-비트 TTD는 2개의 single-pole double-throw(SPDT)와 7개의 double-pole double-throw(DPDT) 스위치로 구현하였으며, 인덕터를 이용하여 반사 특성을 개선하였다. 설계된 8-비트 TTD는 $0.18{\mu}m$ CMOS 공정을 이용하여 제작하였다. 측정된 TTD 회로의 시간 가변 범위는 250 ps이고, 시간 지연 해상도는 약 1 ps이다. 6~18 GHz의 동작 주파수에서 RMS 시간 지연 오차는 11 ps 미만이며, 입출력 반사 손실은 10 dB 이상이다. 공급 전압은 1.8 V이며, 소비 전력은 0.0 mW이다. 칩 면적은 $2.36{\times}1.04mm^2$이다.

• 대한전자공학회논문지SD
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• 제47권8호
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• pp.13-22
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• 2010

Independent-Gate-Mode Double-Gate(IGM-DG) MOSFET은 기존의 bulk-MOSFET에 비해 향상된 채널 제어능력을 가지며, front-게이트와 back-게이트를 서로 다른 전압으로 구동가능하다는 이점을 가진다. 따라서, 이를 이용한 회로설계는 4-terminal의 자유도를 이용함으로써 회로성능의 향상 뿐 아니라 집적도 향상을 기대할 수 있다. 본 논문에서는 IGM-DG MOSFET의 장점을 이용하여 TIA, feedforward LA, 및 OB로 구성된 15Gb/s 광수신기를 설계하고, HSPICE 시뮬레이션을 통한 회로성능 검증 및 외부환경과 소자의 특성변화에 따른 안정성을 검증하였다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1997년도 하계학술대회 논문집 F
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• pp.2104-2106
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• 1997

In order to develop the three phase GTO CSI with double recovery path of commutation energy by passive devices (LCD), we studied the clamping circuit to protect switching device and energy recovery circuit to recover absorbed energy of capacitor and DC inductor. In this paper, we investigated how DC input power is increased or decreased according to energy recovery path with or not in the three phase GTO current source inverter, we used a induction motor as inverter load, and controlled a induction motor with v/f constant control. Experimental results show that dissipated DC power is decreased in $9{\sim}14%$ by double recovery path. We also confirmed that the characteristics is met as compare simulation results with experimental results according to each frequency.

• 대한전기학회논문지:전기기기및에너지변환시스템부문B
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• 제49권9호
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• pp.572-577
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• 2000

This paper describes the test results of a single phase 3kVA high temperature superconducting power transformer. The tapes are made with Bi-2223 and have silver alloy as the matrix. Four double pancake windings are used. Among them two double pancake windings are connected in series for high voltage winding and the others are connected in parallel for low voltage winding. The rated voltage and current of primary winding and secondary winding are 220/110V. 13.7/27.3A. Fundamental characteristics are obtained through short circuit and no load test. The over load capability and characteristics are investigated.

• 한국전자파학회:학술대회논문집
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• 한국전자파학회 2002년도 종합학술발표회 논문집 Vol.12 No.1
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• pp.413-422
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• 2002

A novel photonic bandgap(PBG) structure is proposed and measured for wide bandgap and compact circuit applications. The proposed structure realizes the ultra-wideband bandgap(2-octave) characteristics by superposing two different PBG structures into a coupled double-plane configuration. A low pass filter fabricated using 3-period of the PBG cells shows 2-octave 10 ㏈ stopband from 4.3 to 16.2 ㎓ and 0.2 ㏈ insertion loss in the passband. Moreover, we confirmed that 44∼70 % size reduction can be achieved using the proposed PBG structures. We expect this novel double-plane PBG structure is widely used for compact and wideband circuit applications, such as compact high-efficiency power amplifiers using harmonic tuning techniques.

• JSTS:Journal of Semiconductor Technology and Science
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• 제13권6호
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• pp.647-654
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• 2013

The design and analysis of analog circuit application on CMOS technology are a challenge in deep sub-micrometer process. This paper is a study on the performance value of Double Gate (DG) Metal Oxide Semiconductor Field Effect Transistor (MOSFET) with Gate Stack and the channel engineering Single Halo (SH), Double Halo (DH). Four different structures have been analysed keeping channel length constant. The short channel parameters and different sub-threshold analog figures of merit (FOMs) are analysed. This work extensively provides the device structures which may be applicable for high speed switching and low power consumption application.