• Journal of Electrical Engineering and Technology
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• v.6 no.1
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• pp.1-7
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• 2011

This paper proposes an enhanced noise robust algorithm for fault location on double-circuit transmission line for the case of single line-to-ground (SLG) fault, which uses distributed parameter line model that also considers the mutual coupling effect. The proposed algorithm requires the voltages and currents from single-terminal data only and does not require adjacent circuit current data. The fault distance can be simply determined by solving a second-order polynomial equation, which is achieved directly through the analysis of the circuit. The algorithm, which employs the faulted phase network and zero-sequence network with source impedance involved, effectively eliminates the effect of load flow and fault resistance on the accuracy of fault location. The proposed algorithm is tested using MATLAB/Simulink under different fault locations and shows high accuracy. The uncertainty of source impedance and the measurement errors are also included in the simulation and shows that the algorithm has high robustness.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.6
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• pp.48-55
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• 1998

In this work, the testable CAM(Content Addressable Memory) is designed to perform the test effectively by inserting the ECC(Error Checking Circuit) inside the CAM. The designed CAM has the circuit which is capable of testing the functional faults in read, write, and match operations. In general the test circuit inserted causes the increase of total circuit area, Thus this work, utilizes the new MTA code to reduce the overhead of an area of the built-in test circuit which has a conventional parallel comparator. The designed circuit was verified using the VHDL simulator and the layout was performed using the 0.8${\mu}{\textrm}{m}$ double metal CMOS process. About 30% reduction of a circuit area wad achieved in the proposed CAM using the XOR circuit

• Journal of information and communication convergence engineering
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• v.1 no.4
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• pp.217-222
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• 2003

In this paper, we introduce a hyper-chaos synchronization method using hyper-chaos circuit consist of State-Controlled Cellular Neural Network (SC-CNN). We make a hyper-chaos circuit using SC-CNN with the n-double scroll. A hyper-chaos circuit is created by applying identical n-double scroll or non-identical n-double scroll and Chua's oscillator with weak coupled method to each cell. Hyper-chaos synchronization was achieved using GS(Generalized Synchronization) method between the transmitter and receiver about each state variable in the SC-CNN.

• Journal of Electrical Engineering and Technology
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• v.8 no.3
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• pp.595-602
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• 2013

An air circuit breaker (ACB) with novel double-breaker contact and permanent magnet actuator (PMA) is presented. Three-dimensional (3-D) finite element method (FEM) is employed to compute the electro-dynamic repulsion forces, including the Holm force and Lorentz force, which are acting on the static and movable contacts. The electro-dynamic repulsion forces of different contact pieces are computed, illustrating there is an optimal number of contact pieces for the ACB being studied. The electro-dynamic repulsion force of each contact, which varies from the outer position to the inner position, is also computed. Finally, the contacts of the double-breaker are manufactured according to the analyzed results to validate the simulations.

• Proceedings of the KIEE Conference
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• 1997.07c
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• pp.1038-1040
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• 1997

This paper describes dynamic characteristics test of distance relay and current differential relay using Real Time Digital Simulator on double circuit transmission line. First, The double circuit T/L modeling on RTDS was proposed and the results from the proposed model were compared with those of PSS/E. This comparison shows the possibility of dynamic test using the RTDS. The relay included about 20 test items which are apt to include maloperation of protective relays in critical situations.

• Journal of Sensor Science and Technology
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• v.21 no.1
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• pp.7-12
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• 2012

In this paper, we propose a 4-transistor active pixel sensor(APS) with a novel correlated double sampling(CDS) circuit for the purpose of extending dynamic range. Dual sampling techniques can overcome low-sensitivity and temporal disparity problems at low illumination. To accomplish this, two images are obtained at the same time using different sensitivities. The novel CDS circuit proposed in this paper contains MOS switches that make it possible for the capacitance of a conventional CDS circuit to function as a charge pump, so that the proposed APS exhibits an extended dynamic range as well as reduced noise. The designed circuit was fabricated by using $0.35{\mu}m$ 2-poly 4-metal standard CMOS technology and its characteristics have been evaluated.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.12
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• pp.37-42
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• 1997

A new temperature and supply-insensitive CMOS current reference circuit was designed and tested. Te temperature insensuitivity was achieved by eliminating the mobility dependence term through the multiplication of two current components, one which is proportional to mobility and the other which is inversely proportional to mobility, by using a newly designed CMOS square root circuit. The CMOS sqare root circuit was derived from its bipolar counterpart by operating the MOS transistors in the subthreshold region. The supply insensitivity was achieved by using an internal voltage generator. Te test chip was designed ans sent out for fabrication by using a 2.mu.m double-poly double-metal n-well CMOS technology. When an external voltage source was used for the square root circuit, the maximum variation and the average temperature sensitivity were measured to be 3% and 21.4ppm/.deg.C, respectively, for the temperature range of -15~130.deg.C. The maximum current variation with supply voltage was measured to be 3% within the commerical supply voltage range of 4.5~5.5V at 30.deg. C.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.21 no.7
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• pp.20-28
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• 2007

This paper describes an analytical method to determine the short-term ratings to reliably operate the overhead transmission lines with double-circuit lines when faulting one circuit of the two. As linearizing the thermal equilibrium equation that represents the temperature characteristic of conductors, we show that the linear equation can be easily represented the over-current and it's temperature property during overloading the one line. Generally, it is well hewn that the short-term line ratings should be determined by considering both conductor life and dip. However, most power companies have their own different guides for the short-term ratings. Using the suggested method in this paper, it can be re-accessed the short-term ratings given in Kepco's overhead transmission lines constructed during the past three different periods. As a result, it is verified that the short-term ratings could be increased mil efficiently. Furthermore, it would be directly applied the given method to determine the short-term dynamic line ratings when occurring faults in one of the double-circuit lines, without doing my other actions for the current lines.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.37 no.3
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• pp.44-54
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• 2000

In this paper, a design methodology for the frequency-adaptive negative-delay circuit which can be implemented in standard CMOS memory process is proposed. The proposed negative-delay circuit which is a basic type of the analog SMD (synchronous mirror delay) measures the time difference between the input clock period and the target negative delay by utilizing analog behavior and repeats it in the next coming cycle. A new technology that compensates the auxiliary delay related with the output clock in the measure stage differentiates the Proposed method from the conventional method that compensates it in the delay-model stage which comes before the measure stage. A wider negative-delay range especially prominent in the high frequency performance than that in the conventional method can be realized through the proposed technology. In order to implement the wide locking range, a new frequency detector and the method for optimizing the bias condition of the analog circuit are suggested. An application example to the clocking circuits of a DDR SDRAM is simulated and demonstrated in a 0.6 ${\mu}{\textrm}{m}$ n-well double-poly double-metal CMOS technology.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.6 no.7
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• pp.1064-1068
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• 2002

In this paper, we introduce a hyper-chaos synchronization method using State-Controlled Cellular Neural Network(SC-CNN). We make a hyper-chaos circuit using SC-CNN with the n-double scroll. A hyper-chaos circuit is created by applying identical n-double scrolls with weak coupled method, to each cell. Hyper-chaos synchronization was achieved using drive response synchronization between the transmitter and receiver about each state in the SC-CNN. From the result of the recovery signal through the demodulation method in the receiver, We shown that recovery quality of state variable $$\chi$_3$ is superior to that of ${$\chi$_2}, {$\chi$_1}$ in secure communication.