• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.11a
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• pp.71-71
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• 2009

This paper describes a simple, on-chip CMOS compatible the thin-film inductor applied for the dc-dc converters. A fully CMOS-compatible thin-film inductor with a bottom NiFe core is integrated with the DC-DC converter circuit on the same chip. By eliminating ineffective top magnetic layer, very simple process integration was achieved. Fabricated monolithic thin film inductor showed fairly high inductance of 2.2 ${\mu}H$ and Q factor of 11.2 at 5MHz. When the DC-DC converter operated at $V_{in}=3.3V$ and 5MHz frequency, it showed output voltage $V_{out}=8.0V$, and corresponding power efficiency was 85%.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.31B no.7
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• pp.42-48
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• 1994

In this paper, a low power and high speed flash Analog-to-Digital Converter using current-mode concept is proposed. Current-mode approach offers a number of advantages over conventional voltage-mode approach, such as lower power consumption small chip area improved accuracy etc. Rescently this concept was applied to algorithmic A/D Converter. But, its conversion speed is limited to medium speed. Consequently this converter is not applicable to the high speed signal processing system. This ADC is fabricated in 1.2um double metal CMOS standard process. This ADC's conversion time is measured to be 7MHz, and power consumption is 2.0mW, and differential nonlinearity is less than 1.14LSB and total harmonic distortion is -50dB. The active area of analog chip is about 350 x 550u$m^2$. The proposed ADC seems suitable for a single chip design of digital signal processing system required high conversion speed, high resolution small chip area and low power consumption.

• The Journal of Information Technology
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• v.12 no.2
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• pp.39-47
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• 2009

Residue Number System is used for the purpose of increasing the speed of processing in the many application parts of Image Processing, Computer Graphic, Neural Computing, Digital Signal Processing etc, since it has the characteristic of parallelism and no carry propagation at each moduli. DRNS has the twice RNS Conversion, it is used to decreases the size of the operator in RNS. But it has a week point on the Second Residue to First Residue Conversion time. So, in this paper SRTFR(Second Residue to First Residue) Converter using MRC(Mixed Radix Conversion) is designed to decrease the size of RTB(Residue to Binary) Converter. Since the proposed SRTFR Converter using MRC(Mixed Rdix Convertion) has a pipeline processing. Also, modular operation is applied to at each partitioned SAM(Subtraction and Addition) and MA(Multiplication and addition). In the following study, the more effective design on MA is needed.

• Journal of Power Electronics
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• v.14 no.6
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• pp.1130-1138
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• 2014

This study analyzes a ladder multilevel converter (double ladder topology) with the use of a new averaging modeling technique. This technique introduces an analytical method to compute for the switching losses and is used to conduct an in-depth analysis of the influence of the switching frequency and parasitic resistance of components on converter efficiency. The obtained results enable the selection of switches and switching frequency to minimize losses. Moreover, simulation results and experimental measurements validate the analytical calculations.

• 제어로봇시스템학회:학술대회논문집
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• 2005.06a
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• pp.782-785
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• 2005

This article introduces technique to reduce harmonic by using the $5^{th}$ and $7^{th}$ harmonic tune filter and line reactor in the comparison to the technique of intervening firing method at the pulse of the 6-pulse phase-controlled converter in every 1/6 period. The design of the technique introduced in this article is to reduce the harmonic distortion of the current and the voltage resulted from three-phase thyristor phase-controlled converter. The waveform obtained from the experiment was analyzed on the spectrum of the current, voltage and the total harmonic distortion. The double firing method causes zero vectors of output voltage and input current. Designing the mechanism of the converter based on the idea of Park Vector Theory, the number of harmonic distortion in the intervening firing method were compared to those in normal firing method.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.5
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• pp.615-623
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• 2016

The paper describes a hysteretic buck converter including a differentiator and an adaptive hysteresis window controller. Differentiating the feedback signal achieves ultra-fast switching of the buck converter. The adaptive hysteresis window control allows a monotonous operation with predictable noise spectrum, and gives way to efficient design for variable supply and output voltages. The measurement results in a $0.13-{\mu}m$ CMOS process indicated that the switching frequency became double times higher, and the voltage ripple was reduced by up to 69%. They also indicated that the normalized switching frequency variation was reduced by 74% with variable $V_{DD}$ and by 63% with variable $V_{OUT}$. The power efficiency was improved by 3.5% depending on loading condition.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.443-444
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• 2008

A double-balanced frequency up-converter using the Gilbert cell structure has been designed with the TSMC $0.18\;{\mu}m$ CMOS library. The frequency up-converter consists of a Mixer core and IF / LO balun. Frequency Up-converter exhibits a 3.4 dB conversion gain with a - 7.6 dBm $P_{1dB}$ for IF power of -10 dBm and LO power of 0 dBm inputs. It also exhibits 92.2 % modulation depth as a ASK modulator.

• Journal of Power Electronics
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• v.7 no.1
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• pp.55-63
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• 2007

This paper proposes a simple unity power factor zero-voltage-transition (ZVT) pulse-width-modulated (PWM) single-phase rectifier, which features reduced switching and conduction losses. The switching loss reduction is achieved by a simple auxiliary commutation circuit, and the conduction loss reduction is achieved by employing a single-stage converter, rather than a typical double-stage converter comprising of a front-end rectifier and a boost rectifier. Furthermore, thanks to good features such as a simple PWM control at constant frequency, low switch stress, low Var rating of commutation circuits, and simple power circuit structure, it is suitable for high power applications. The principles of operation are explained in detail, and a major characteristics analysis and the experimental results of the new converter are also included in this paper.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.12
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• pp.98-107
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• 1993

This paper describes a design of a multi-bit oversampling noise-shaping D/A converter which achieves a resolution of 12 bits using oversampling technique. In the architecture the essential block which determines the whole accuracy is the analog internal D/A converter, and the designed charge-integration internal D/A converter adopts a differential structure in order to minimize the reduction of the resolution due to process variation. As the proposed circuit is driven by signal clocks which contains the information of the data variation from the noise-shaping coder, it minimizes the disadvantage of a charge-integration circuit in the time axis. In order to verify the circuit, it was integrated with the active area of 950$\times$650${\mu}m^{2}$ in a double metal 1.5-$\mu$m CMOS process, and testified that it can achieve a S/N ratio of 75 dB and a S/(N+D) ratio of 60 dB for the signal bandwidth of 9.6 kHz by the measurement with a spectrum analyzer.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.6
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• pp.58-70
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• 1997

In this paper, an 8bit CMOS low power, high-speed current-mode folding and interpolation A/D converter is designed with te LG semicon $0.8\mu\textrm{m}$ N-well single-poly/double-metal CMOS process to be integrated into a portable image signal processing system such as a digital camcoder. For good linearity and low power consumption, folding amplifiers and for high speed performance of the A/D converter, analog circuitries including folding block, current-mode interpolation circuit and current comparator are designed as a differential-mode. The fabricated 8 bit A/D converter occupies the active chip area of TEX>$2.2mm \times 1.6mm$ and shows DNL of $\pm0.2LSB$, INL of <$\pm0.5LSB$, conversion rate of 40M samples/s, and the measured maximum power dissipation of 33.6mW at single +5V supply voltage.