• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.15 no.4
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• pp.143-152
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• 2016

In this paper, a MMIC double balanced mixer that can be applied to the tele-communication band is designed and LO power optimization for the mixer is discussed. The chip of the MMIC double-balanced mixer is fabricated on GaAs substrate with the size of $4{\times}4mm^2$. Optimization study of LO power for the MMIC double-balanced mixer proposed in this paper is conducted for the Input IP3 (IIP3) regarding on the linearity of the input signal. When LO power level of+16 dBm is applied to the mixer, IIP3 is obtained to be approximately 23.2 dBm, which is the most outstanding characteristic.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.2 no.2 s.3
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• pp.97-101
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• 2003

A MMIC (monolithic microwave integrated circuit) mixer chip using the Schottky diode of an InGahs/CaAs p-HEMT process has been developed for the receiver down converter of Ku-band. A different approach to the MMIC mixer structure is applied for reducing the chip size by the exchange of ports between If and LO. This MMIC covers with RF (14.0 - 14.5 GHz) and If (12.252 - 12.752 GHz). According to the on-wafer measurement, the miniature (3.3X3.0 m) MMIC mixer demonstrates conversion loss below 9.8 dB, RF-to-IF isolation above 23 dB, LO-to-IF isolation above 38 dB, respectively.

• JSTS:Journal of Semiconductor Technology and Science
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• v.1 no.4
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• pp.248-252
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• 2001

A noble single-ended input, double-balanced mixer topology is proposed. The mixer incorporates the common-source amplifier input stage with inductive degeneration for impedance matching. The analysis based on simulations shows that the overall performance of the mixer is excellent and is adjustable by varying the input transistor size to give best characteristics for the given linearity specifications.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.13 no.8
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• pp.764-768
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• 2002

In this paper, a double balanced gilbert cell MMIC mixer was realized in Tachyonics SiGe HBT technology. The fabricated mixer has 17 dB conversion gain, 9.8 dB noise figure, -4.2 dBm output 1 dB compression point, -27 dBc RF to IF isolation, and the good input, output matching characteristics. It draws 10 mA from a 3 V supply. The simulation and the measured results are closer to each other, which confirms accuracy of the model library and reliability of the process.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.15 no.3
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• pp.258-264
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• 2004

In this paper, MMIC double balanced star mixer for 40 ㎓ was implemented on GaAs substrate with backside vias. In the design of the MMIC mixer, the design of balun and diode was required. A novel balun structure using microstrip to CPS was presented. The 40 ㎓ balun was designed based on the design experience of the scale-down balun by 2 ㎓. The balun may be suitable for fabrication in MMIC process with backside via and can easily be applied for DBM(Double Balanced Mixer). A Schottky diode was designed and implemented using p-HEMT process considering the compatability with other high frequency MMIC's fabricated on p-HEMT base process. Finally, the double balanced star mixer was fabricated using the balun and the p=HEMP Schottky diode. The measured performance of mixer shows 30 ㏈ conversion loss at 18 ㏈m LO power. This insufficient performance is caused by the unwanted diode at AlGaAs junction in vertical structure of p-HEMT. If the p-HEMT's gate is recessed to AlGaAs layer, and so the diode is eliminated, the mixer's performances will be improved.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.531-532
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• 2008

In this paper, we present the comparison of the CMOS Double-Balanced Mixer for WLAN applications using the tail current source and not using it at the same current. The mixers are derived from the Gilbert cell mixer and have been simulated by using TSMC $0.18{\mu}m$ RF CMOS technology.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.2
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• pp.227-231
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• 2004

A MMIC (Monolithic Microwave Integrated Circuit) mixer chip using the schottky diode of InGaAs/CaAs p-HEMT process has been developed for receiver down converter of Ka-band. A different approach of MMIC mixer structure is applied for reducing the chip size by the exchange of ports between IF and LO. This MMIC covers with RF (30.6∼31.0㎓)and IF (20.8∼21.2㎓). According to the on-wafer measurement, the MMIC mixer with miniature size of 3.0mm1.5mm demonstrates conversion loss below 7.8㏈, LO-to-RF isolation above 27㏈, LO-to-IF isolation above 19㏈ and RF-to-IF isolation above 39㏈, respectively.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2003.11a
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• pp.630-637
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• 2003

In this paper, a DBM(double balanced mixer) of 2 GHz is implemented on FR4(h=1.6mm, ${\epsilon}_r=4.6$) substrate. The structure of double balanced mixer requires, in general, two talons and a quad diode. For balun, a novel planar balun using microstrip to CPS(Coplanar Strip) is suggested and designed. The suggested balun shows the phase imbalance of $180^{\circ}{\pm}1.5^{\circ}$ and the amplitude imbalance of ${\pm}0.2 dB$ for 1.5 to 2.5 GHz. Using the balun, DBM is successfully implemented, and the measured conversion loss of up/down converter show about 6 dB over the bandwidth. The balun may be applicable for MMIC(Monolithic Microwave Integrated Circuit) DBM with the process supporting backside via though more study.

• Journal of electromagnetic engineering and science
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• v.8 no.3
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• pp.91-95
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• 2008

This paper presents a direct-conversion I/Q up-mixer block, which supports $3{\sim}5$ GHz ultra-wideband(UWB) applications. It consists of a VI converter, a double-balanced mixer, a RF amplifier, and a differential-to-single signal converter. To achieve wideband characteristics over $3{\sim}5$ GHz frequency range, the double-balanced mixer adopts a shunt-peaking load. The proposed RF amplifier can suppress unwanted common-mode input signals with high linearity. The proposed direct-conversion I/Q up-mixer block is implemented using $0.18-{\mu}m$ CMOS technology. The measured results for three channels show a power gain of $-2{\sim}-9$ dB with a gain flatness of 1dB, a maximum output power level of $-7{\sim}-14.5$ dBm, and a output return loss of more than - 8.8 dB. The current consumption of the fabricated chip is 25.2 mA from a 1.8 V power supply.

• International Journal of Internet, Broadcasting and Communication
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• v.15 no.3
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• pp.122-128
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• 2023

This paper proposes two kinds of single-balanced direct conversion quadrature receivers using selfoscillating LMVs in which the voltage-controlled oscillator (VCO) itself operates as a mixer while generating an oscillation. The two LMVs are complementary coupled and series coupled to generate the quadrature oscillating signals, respectively. Using a 65 nm CMOS technology, the proposed quadrature receivers are designed and simulated. Oscillating at around 2.4 GHz frequency, the complementary coupled quadrature receiver achieves the phase noise of -28 dBc/Hz at 1KHz offset and -109 dBc/Hz at 1 MHz offset frequency. The other series coupled receiver achieves the phase noise of -31 dBc/Hz at 1KHz offset and -109 dBc/Hz at 1 MHz offset frequency. The simulated voltage conversion gain of the two single-balanced receivers is 37 dB and 45 dB, respectively. The double-sideband noise figure of the two receivers is 5.3 dB at 1 MHz offset. The quadrature receivers consume about 440 μW dc power from a 1.0-V supply.