• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.5C
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• pp.506-511
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• 2002

In this paper, waveguide-based power combiner using conventional slotline-to-microstrip transition was proposed at Ka-band. The proposed 2-way and 4-way power combiner consist of waveguide-to-slotline transition, two or four slotline-to-microstrip transitions, and impedance matching networks. Their structures were simulated and optimized by 3-D FEM simulation. The 2-way power combiner showed a very low back-to-back insertion loss of 1.0 dB and return loss better than 15 dB from 25.7 GHz to 29.8 GHz except the resonant frequency. The 2-way power combining approach was extended to 4-way power combining using slotline tee junction. The 4-way power combiner showed the similar performance to that of 2-way power combiner with 2 GHz smaller bandwidth.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.12
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• pp.57-63
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• 2016

This paper describes implementation of the RF frequency synthesizer with $0.18{\mu}m$ silicon CMOS technology being used as an application of the IEEE802.15.4g SUN sensor node transceiver modules. Design of the each module like VCO, prescaler, 1/N divider, ${\Delta}-{\Sigma}$ modulator, and common circuits of the PLL has been optimized to obtain high speed and low noise performance. Especially, the VCO has been designed with NP core structure and 13 steps cap-bank to get high speed, low noise, and wide band tuning range. The output frequencies of the implemented synthesizer is 1483MHz~2017MHz, the phase noise of the synthesizer is -98.63dBc/Hz at 100KHz offset and -122.05dBc/Hz at 1MHz offset.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.41 no.4
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• pp.31-39
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• 2004

The ARM7 TDMI microprocessor employ a software routine iteration method in order to handle integer division operation, but this method has long execution time and many execution instruction. In this paper, we proposed ARM7 TDMI microprocessor with integer division instruction. To make this, we additionally defined UDIV instruction for unsigned integer division operation and SDIV instruction for signed integer division operation, and proposed ARM7 TDMI microprocessor data Path to apply division algorithm. Applied division algorithm is nonrestoring division algorithm and additive hardware is reduced using existent ARM data path. To verify the proposed method, we designed proposed method on RTL level using HDL, and conducted logic simulation. we estimated the number of execution cycles and the number of execution instructions as compared proposed method with a software routine iteration method, and compared with other published integer divider from the number of execution cycles and hardware size.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.2
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• pp.27-35
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• 2016

A Low jitter dual output frequency synthesizer for smart audio devices is described in this paper. It has been fabricated in a 1.8 V Dongbu $0.18-{\mu}m$ CMOS process. Output frequency is controlled by 3 rd order Sigma-Delta Modulation and digital divider. The frequency synthesizer has a size of $0.6mm^2$, frequency range of 0.6-200 MHz, loop bandwidth of 350 kHz, and rms jitter of 11.4 ps-21.6 ps.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.17 no.8 s.111
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• pp.732-738
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• 2006

Divide-by-2 and divide-by-4 circuits which can operate up to 10 GHz are designed. A design method used in these circuits is the TSPC(True Single Phase Clocking) topology. The structure of the TSPC dividers is very simple because they need only a single clock and purely consist of smalt sized cmos devices. Through measurements, we find the fact that in proportion to the bias voltage, the free running frequency increases and the operation region also moves toward a higher frequency region. For operating conditions of bias voltage $3.0{\sim}4.0V$, input power 16dBm and dcoffset $1.5{\sim}2.0V$, 5 GHz and 2.5 GHz output signals divided by 2 and 4 are measured. The layout size of the divide-by-2 circuit is about $500{\times}500 um^2$($50{\times}40um^2$ except pad interconnection part).

• Journal of electromagnetic engineering and science
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• v.13 no.3
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• pp.178-185
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• 2013

This paper introduces a high-efficiency, high-gain, broadband quasi-Yagi antenna, and its four-element array for use in 60-GHz wireless communications. The antenna was fed by a microstrip-to-slotline transition consisting of a curved microstripline and a circular slot to allow broadband characteristics. A corrugated ground plane was employed as a reflector to improve the gains in the low-frequency region of the operation bandwidth, and consequently, to reduce variation. The single antenna yielded an impedance bandwidth of 49 to 69 GHz for $|S_{11}|$ <-10dB and a gain of >12.0 dBi while the array exhibited a bandwidth of 52 to 68 GHz and a gain greater than 15.0 dBi. Both proposed designs had small gain variations (${\pm}0.5$ dBi) and high radiation efficiency (>95%) in the 60-GHz bands. The features of the proposed antenna were validated by designing, fabricating, and testing a scaled-up configuration of the single antenna at the 15-GHz band. The measurements resulted in an impedance bandwidth of 13.0 to 17.5 GHz for $|S_{11}|$ <-10dB, a gain of 10.1 to 13.2 dBi, and radiation efficiency in excess of 88% within this bandwidth. Additionally, the 15-GHz antenna yielded quite symmetric radiation profiles in both E- and H-planes, with a high front-to-back ratio.

• Proceedings of the Korean Society of Medical Physics Conference
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• 2002.09a
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• pp.331-334
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• 2002

It has been reported that maximum-likelihood position-estimation (MLPE) algorithms offer advantages of improved spatial resolution and linearity over conventional Anger algorithm in gamma cameras. The purpose of this study is to evaluate the performances of the noise models, Poisson and Gaussian, in MLPE for the localization of photons in a small gamma camera (SGC) using NaI(Tl) plate and PSPMT. The SGC consists of a single NaI(Tl) crystal, 10 cm diameter and 6 mm thick, optically coupled to a PSPMT (Hamamatsu R3292-07). The PSPMT was read out using a resistive charge divider, which multiplexes 28(X) by 28(Y) cross wire anodes into four channels. Poisson and Gaussian based MLPE methods have been implemented using experimentally measured light response functions. The system resolutions estimated by Poisson and Gaussian based MLPE were 4.3 mm and 4.0 mm, respectively. Integral uniformities were 29.7% and 30.6%, linearities were 1.5 mm and 1.0 mm and count rates were 1463 cps and 1388 cps in Poisson and Gaussian based MLPE, respectively. The results indicate that Gaussian based MLPE, which is convenient to implement, has better performances and is more robust to statistical noise than Poisson based MLPE.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.6
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• pp.43-55
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• 2013

In this paper, we propose a cylindrical active phased array antenna of Beam Steering Characteristics in the horizontal plane(H-plane) and vertical plane(E-Plane) on the cylinder form array structure. We design the bent dipole antenna of the cylindrical array structure adapted excellent mutual-coupling characteristics, designed and manufactured the cylindrical array antennas and power combiner/divider unit for power dividing and combining on the antenna. The radiating elements array spacing of Cylindrical array antenna were determined to avoid grating lobes at half power beam steering. Beam steering of the antenna was implemented with 6-bit phase shifter in the transceiver and have been designed based on the characteristics the antenna beam steering at -24 degrees to 24 degrees horizontal, vertical 0 degrees to 36 degrees beam steering. A cylindrical active phased array antenna that produced for verification the performance of the antenna are measured radiation characteristics in accordance with beam steering at L-Band.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.4 s.346
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• pp.38-48
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• 2006

In this paper, we developed a hardware architecture of Reed-Solomon RS(255,239) decoder for the DMB mobile terminals. The DMB provides multimedia broadcasting service to mobile terminals, hence it should have small dimension for low power and short decoding delay for real-time processing. We modified Euclid algorithm to apply it to the key equation solving which is the most complicated part of the RS decoding. We also designed a small finite field divider to avoid the use of large Inverse-ROM table, and it consumed 17 clocks. After synthesis with Synopsis on Samsung STD130 $0.18{\mu}m$ Standard Cell library, the Euclid block had 30,228 gates and consumed 288 clocks, which gave the 25% reduced area compared to other existing designs. The size of the entire RS decoder was about 45,000 gates.

• Journal of Sensor Science and Technology
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• v.6 no.2
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• pp.137-144
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• 1997

In this paper, the design of a 10-bit 40-MS/s pipelined A/D converter is implemented to achieve low static power dissipation of 70 mW at the ${\pm}2.5\;V$ or +5 V power supply environment for high speed applications. A 1.5 b/stage pipeline architecture in the proposed ADC is used to allow large correction range for comparator offset and perform the fast interstage signal processing. According to necessity of high-performance op amps for design of the ADC, the new op amp with gain boosting based on a typical folded-cascode architecture is designed by using SAPICE that is an automatic design tool of op amps based on circuit simulation. A dynamic comparator with a capacitive reference voltage divider that consumes nearly no static power for this low power ADC was adopted. The ADC implemented using a $1.0{\mu}m$ n-well CMOS technology exhibits a DNL of ${\pm}0.6$ LSB, INL of +1/-0.75 LSB and SNDR of 56.3 dB for 9.97 MHz input while sampling at 40 MHz.