• Journal of the Korean Institute of Telematics and Electronics D
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• v.35D no.11
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• pp.85-90
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• 1998

A 1 4 polymeric optical power divider based on the multimode interference effect is designed and fabricated. The two dimensional finite difference beam propagation method has been utilized in designing the device. Polymers used for the core layer and the cladding layer are Cyclotene-3022 and UV-15, respectively. The device is fabricated by the reactive ion etching method. The splitting ratio of the fabricated device is 0.93 : 1.00 : 0.93 : 0.90 for TE mode and 0.84 : 0.94 : 1.00 : 0.83 for TM mode. The advantages of this device are small size and low polarization-dependence.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.9
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• pp.270-275
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• 2012

This paper describes design of a variable-N frequency synthesizer for RF PLL with $0.13{\mu}m$ silicon CMOS technology being used as an application of the UWB system like MBOA. To get good performance of speed and noise super dynamic circuits was used, and to get variable-N division ratio MOSFET switching circuits was used. Especially to solve narrow bandwidth problem of the dynamic circuits load resistance value of unit divider block was varied. Simulation results of the designed circuit shows very fast and wide operation characteristics as 5~26GHz frequency range.

• The KSFM Journal of Fluid Machinery
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• v.19 no.1
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• pp.37-44
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• 2016

In this study, a parametric study of a centrifugal pump with double volute has been performed numerically using three-dimensional Reynolds-averaged Navier-Stokes equations. The shear stress transport model was selected as turbulence closure through turbulence model test. The finite volume method and unstructured grid system were used for the numerical analysis. The optimal grid system in the computational domain was determined through a grid dependency test. The expansion coefficient, circumferential and radial starting positions and length of divider were selected as the geometric parameters to be tested. And, the hydraulic efficiency and the radial thrust coefficient were considered as performance parameters. It was found that the radial thrust and hydrualic efficiency are more sensitive to the expansion angle and circumferential starting position of the divider than the other geometrical parameters.

• Journal of electromagnetic engineering and science
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• v.17 no.3
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• pp.138-146
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• 2017

A phase-locked dielectric resonator oscillator (PLDRO) is an essential component of millimeter-wave communication, in which phase noise is critical for satisfactory performance. The general structure of a PLDRO typically includes a dual loop of digital phase-locked loop (PLL) and analog PLL. A dual-loop PLDRO structure is generally used. The digital PLL generates an internal voltage controlled crystal oscillator (VCXO) frequency locked to an external reference frequency, and the analog PLL loop generates a DRO frequency locked to an internal VCXO frequency. A dual loop is used to ease the phase-locked frequency by using an internal VCXO. However, some of the output frequencies in each PLL structure worsen the phase noise because of the N divider ratio increase in the digital phase-locked loop integrated circuit. This study examines the design aspects of an interconnected PLL structure. In the proposed structure, the voltage tuning; which uses a varactor diode for the phase tracking of VCXO to match with the external reference) port of the VCXO in the digital PLL is controlled by one output port of the frequency divider in the analog PLL. We compare the proposed scheme with a typical PLDRO in terms of phase noise to show that the proposed structure has no performance degradation.

• The KSFM Journal of Fluid Machinery
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• v.10 no.2 s.41
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• pp.32-40
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• 2007

The present study investigated local pressure drop in a rotating smooth square duct with turning region. The duct has a hydraulic diameter $(D_h)$ of 26.7mm and a divider wall of 6.0mm or $0.225D_h$. The distance between the tip of the divider and the outer wall of the duct is $1.0D_h$. The Reynolds number (Re) based on the hydraulic diameter is kept constant at 10,000, and the rotation number (Ro) is varied from 0.0 to 0.20. The pressure coefficient distribution $(C_p)$, the friction factor (f) and the thermal performance $({\eta})$ are presented on the leading, the trailing and the outer surfaces. It is found that the curvature of the $180^{\circ}-turn$ produces Dean vortices that cause the high pressure drop in the turning region. The duct rotation results in the pressure coefficient discrepancy between the leading and trailing surfaces. That is, the high pressure values appear on the trailing surface in the first-pass and on the leading and side surfaces in the second-pass. As the rotation number increases, the pressure discrepancy enlarges. In the fuming region, a pair of the Dean vortices in the stationary case transform into one large asymmetric vortex cell, and then the pressure drop characteristics also change.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.1
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• pp.56-61
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• 2011

This paper describes design of a programmable frequency synthesizer for RF PLL with $0.18{\mu}m$ silicon CMOS technology being used as an application of the UWB system like MBOA. To get good performance of speed and noise super dynamic circuits was used, and to get programmable division ratio switching circuits was used. Especially to solve narrow bandwidth problem of the dynamic circuits load resistance value of unit divider block was varied. Simulation results of the designed circuit shows very fast and wide operation characteristics as 1~14GHz frequency range.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.10 no.5
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• pp.967-971
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• 2009

The histogram equalization algorithm is the most crucial algorithm for image enhancement. Since its direct hardware implementation always requires a divider or multiplier, its implementation cost tends to increas as the image resolution is increased or diverse image resolutions are handled. In this paper, we propose a divider-free reconstruction of histogram equalization algorithm and the corresponding hardware architecture. The logic synthesis results show that the proposed scheme can reduce the logic gate count by 84.2% compared to the conventional implementation example when the UXGA resolution is considered.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.2B
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• pp.145-150
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• 2002

This paper presents an implementation methodology of unified PCS base station system which, is capable of providing PCS services for 3 PCS carriers concurrently. We have built up an unified PCS BTS using a unification module, which is consisted of a multi-channel combiner, duplexer, LNA, power divider, feeder line, and a common set of antennas. PCS unification module is featured with wide-band and high power handling capability and electrical characteristics like insertion loss, isolation have been greatly improved. It was shown that performance of the system in terms of Ec/Io and mobile receive power within the total 30MHz PCS frequency range is uniformly acceptable and measured signal quality and coverage are equivalent to that of the individual PCS base station.

• Proceedings of the KIEE Conference
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• 2001.07c
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• pp.1612-1615
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• 2001

포항 방사광 가속기 2.5 GeV의 전자선형 가속기는 마이크로웨이브 발생원으로써 80 MW 클라이스트론(klystron) 11대와 입사부에 65 MW 클라이스 트론 1대를 사용한다. 전자빔 에너지의 효율적인 제어를 위하여 고출력 클라이스트론의 RF 전력과 입력 빔의 전력을 정확하게 측정해야 하며 응답특성이 양호한 측정장치와 정밀한 측정이 요구된다. 클라이스트론에 공급되는 전력은 캐소드에 인가되는 전압과 전류의 측정치로 계산된다. 비록 빔 전압측정에서의 작은 오차일지라도 클라이스트론 RF 출력 전력의 결과값에 큰 영향을 미친다. 따라서, 빔 전압의 측정시에 정확한 측정을 위하여 특별한 주의가 요구된다. 고전압 펄스전원장치 인 모듈레이터 (modulator)에서 발생되는 수백 kV(350-400 kV)의 전압을 측정하기 위하여 커패시터의 용량비로 입력전압을 분압하는 용량성 분압기(capacitive voltage divider, CVD)가 사용된다. 고압측 분압용 표준 콘덴서의 정전용량을 결정하는 주요인자는 고전압 절연유의 유전율(dielectric constant)이다. 그러므로, 측정범위 내의 전압, 주파수, 온도에 대하여 정전용량의 변화율이 작도록 설계하여야 한다. 본 논문에서는 펄스형 고전압 신호 측정을 위한 용량성 전압 분배기의 측정원리, 설계분석, 교정시험, 절연유의 온도변화에 따른 정전용량 변화 특성에 대한 실험 결과를 고찰하고자 한다.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.46 no.4
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• pp.40-45
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• 2009

In This Paper, New Efficient Arithmatic Logic Unit Design for Calculating Error Values of Reed Solomon Decoder is described. Error Values are solved by solving Linear system of Equations, So called Newtonian set of identity equations. Here We Need Galois Multiplier, Adder, Divider on GF($2^8$) field. We prove how the Hardware circuits are improved better than the classical circuits. The method to find error location is not covered here, since many other researchers have already deeply studied it.