• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.1A
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• pp.104-112
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• 2005

Some design techniques for high speed and low power pipelined 8-bit ADC are described. To perform high-speed operation with relatively low power consumption, open loop architecture is adopted, while closed loop architecture (with MDAC) is used in conventional pipeline ADC. A distributed track and hold amplifier and a cascading structure are also adopted to increase the sampling rate. To reduce the power consumption and the die area, the number of amplifiers in each stage are optimized and reduced with proposed zero-crossing point generation method. At 500-MHz sampling rate, simulation results show that the power consumption is 210mW including digital logic with 1.8V power supply. And the targeted ADC achieves ENOB of about 8-bit with input frequency up to 200-MHz and input range of 1.2Vpp (Differential). The ADC is designed using a $0.18{\mu}m$ 6-Metal 1-Poly CMOS process and occupies an area of $900{\mu}m{\times}500{\mu}m$

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.12
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• pp.2633-2640
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• 2009

We design a small-area, low-power, and high-speed EEPROM for touch screen controller IC. As a small-area EEPROM design, a SSTC (side-wall selective transistor) cell is proposed, and high-voltage switching circuits repeated in the EEPROM core circuit are optimized. A digital data-bus sensing amplifier circuit is proposed as a low-power technology. For high speed, the distributed data-bus scheme is applied, and the driving voltage for both the EEPROM cell and the high-voltage switching circuits uses VDDP (=3.3V) which is higher than the logic voltage, VDD (=1.8V), using a dual power supply. The layout size of the designed 128-KBit EEPROMIP is $662.31{\mu}m{\times}1314.89{\mu}m$.

• 제어로봇시스템학회:학술대회논문집
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• 2004.08a
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• pp.1972-1974
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• 2004

This paper describes the high pass filter with notch charecteristics. The proposed circuits configuration consists of two uniformly distributed RC line (herein after is called URC) and two gain amplifiers ($K_1$ and $K_2$). With the appropriate $K_1$ and $K_2$ , the circuit has a steeper slope of magnitude response at pass band steeper than using a single gain amplifier.

• Journal of the Optical Society of Korea
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• v.5 no.1
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• pp.5-8
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• 2001

In this work, we studied the effect of chirped grating on optical bistability in λ/4-shifted semiconductor distributed-feedback(DFB) devices, such as an etalon with nonlinear mirrors, a λ/4-shifted DFB waveguide and aλ/4-shifted DFB laser amplifier. We found that chirped DFB devices exhibit bistable switching at a lower input power.OCIS code : 050.2770, 190.1450, 190.5970, 230.0230.

• Journal of Power Electronics
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• v.13 no.1
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• pp.51-58
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• 2013

This paper proposes the power conversion mechanism of a bailer-charge-transfer zero-current-switching (CT-ZCS) circuit. The operation modes are analyzed and researched using state trajectory equations. The topology of CT-ZCS based on soft-switching inverters offers some merits such as: tracking the input reference signal dynamically, bearing load shock and short circuit, multiplying inverter N+1 redundancy parallel, coordinating power balance for easy control, and soft-switching commutation for high efficiency and large capacity. These advantages are distinctive from conventional inverter topologies and are especially demanded in AC drives: new energy generation and grid, distributed generation systems, switching power amplifier, active power filter, and reactive power compensation and so on. Prototype is manufactured and experiment results show the feasibility and dynamic voltage-tracking characteristics of the topology.

• Proceedings of the KIEE Conference
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• 2004.11b
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• pp.147-150
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• 2004

본 논문에서는 분산전원 계통을 모의하기 위한 시뮬레이터의 설계와 시험에 대한 내용을 제시하고자 한다. 제시하고자 하는 시뮬레이터는 RTDS(Real Time Digital Simulator)와 전력 증폭기(power amplifier)로 구성된다. RTDS 부분은 분산전원이 적용되는 계통의 모의와 분산전원의 전원부 모의를 위해 사용되며 전력 증폭기는 RTDS에 의해 모의된 전력 계통의 모선 전압 출력과 분산전원 전원부의 전압 출력을 증폭하기 위하여 사용된다. 시뮬레이터 구성을 위해 사용되는 RTDS의 구성과 제작된 전력 증폭기의 사양과 동작시험에 대한 결과를 제시하고자 한다. 개발된 시뮬레이터는 분산전원의 동적 및 정적 성능 평가를 위한 시험 시스템 개발에 적용될 수 있다.

• Journal of the Optical Society of Korea
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• v.12 no.4
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• pp.351-354
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• 2008

We demonstrate an ultra-dense wavelength-division- multiplexed (UD-WDM) passive optical network (PON) where 12.5-GHz spaced 1 GbE ${\times}$ 256 optical channels are distributed using 12.5- and 200-GHz arrayed waveguide gratings in series. For the generation of upstream signals, we use reflective semiconductor optical amplifiers. We use two optical fiber amplifiers at the optical line terminal to amplify downstream and upstream channels.

• ETRI Journal
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• v.38 no.4
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• pp.665-674
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• 2016

We designed and fabricated a semiconductor optical amplifier-integrated dual-mode laser (SOA-DML) as a compact and widely tunable continuous-wave terahertz (CW THz) beat source, and a pin-photodiode (pin-PD) integrated with a log-periodic planar antenna as a CW THz emitter. The SOA-DML chip consists of two distributed feedback lasers, a phase section for a tunable beat source, an amplifier, and a tapered spot-size converter for high output power and fiber-coupling efficiency. The SOA-DML module exhibits an output power of more than 15 dBm and clear four-wave mixing throughout the entire tuning range. Using integrated micro-heaters, we were able to tune the optical beat frequency from 380 GHz to 1,120 GHz. In addition, the effect of benzocyclobutene polymer in the antenna design of a pin-PD was considered. Furthermore, a dual active photodiode (PD) for high output power was designed, resulting in a 1.7-fold increase in efficiency compared with a single active PD at 220 GHz. Finally, herein we successfully show the feasibility of the CW THz system by demonstrating THz frequency-domain spectroscopy of an ${\alpha}$-lactose pellet using the modularized SOA-DML and a PD emitter.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.27 no.3
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• pp.277-283
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• 2016

In this paper, a system of self-interference signal cancelation for in-band full duplex has been implemented and tested in RF/analog region. The system performance has been evaluated with NI5791 platform and NI Flex RIO. Due to the low power level of the NI5791, the RF signal is amplified by SKYWORKS SE2565T power amplifier. A circulator is used to feed the antenna both the transmitter and receiver. The RF FIR filter is designed by twelve delay taps in two different groups, and the interval between each delay tap is designed to have 100 ps. The amplified signal is distributed to antenna and the FIR filter by use of a 10 dB directional coupler. The tap coefficients of the RF FIR filter are tuned to estimate the self-interference signal coming from antenna reflection and the leakage of the circulator, and the self-interference signal is subtracted. The system is test with 802.11a/g 20 MHz OFMD at 2.56 GHz, and the output power of the amplifier of 0 dBm. The self-interference signal is canceled out by 53 dB.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2003.05a
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• pp.787-790
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• 2003

A 4-wavelength optical transceiver system is designed and implemented by using 4 OADMs (optical add-drop multiplexers), WDMs, and optical transceivers. In this new system, the wavelengths of 1510 nm and 1530 nm are used for upload and download signals, respectively, as well as the wavelengths of 1550 nm and 1310 nm which have been utilized in a 2-wavelength optical transceiver systems. The 4-wavelength optical module shows very encouraging pass characteristics of about - 5 dB and isolation characteristics of less than -40 dB, which is configured with two OADMs, 4 couplers, and WDM couplers by fusion splicing. Noise figure (NF) of the one-stage balanced amplifier designed and fabricated for receiver module is 0.38 dB and the amplifying gain is 14.2 dB. S$_{11}$, S$_{22}$ and input, output VSWR are -28.81 dB, -32.08 dB, 1.05 : 1, 1.08 : 1, respectively.y.