• The Journal of Advanced Prosthodontics
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• v.11 no.2
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• pp.95-104
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• 2019

PURPOSE. To evaluate the effect of surface treatments and repair materials on the shear bond strength and to measure the fracture toughness of CAD/CAM provisional restoration materials. MATERIALS AND METHODS. Four CAD/CAM (3D printing: Nextdent C&B and ZMD-1000B Temporary, CAD/CAM resin block: Yamahachi PMMA disk and Huge PMMA block) and four conventional (monometacrylate: Jet and Alike, dimetacrylate: Luxatemp and Protemp 4) materials were selected to fabricate disk-shaped specimens and divided into six groups according to surface treatment (n=10). CAD/CAM materials were repaired with Jet or Luxatemp, while conventional materials were repaired with their own materials. The shear bond strength was measured by using universal testing machine. Ten rectangular column-shaped specimens for each material were fabricated to measure the fracture toughness by single edge v notched beam technique. Statistical analysis was performed by one-way ANOVA. RESULTS. The highest shear bond strength of CAD/CAM materials was achieved by SiC paper + sandblasting. It was also accomplished when repairing 3D printing materials with Luxatemp, and repairing CAD/CAM resin blocks with Jet. Yamahachi PMMA disk showed the highest fracture toughness. Nextdent C&B showed the lowest fracture toughness value but no statistically significant difference from Alike and Luxatemp (P>.05). CONCLUSION. In order to successfully repair the CAD/CAM provisional restoration, mechanical surface treatment and appropriate repair material according to the CAD/CAM material type should be selected. The CAD/CAM provisional materials have proper mechanical properties for clinical use as compared to conventional materials.

• Journal of KIISE:Computer Systems and Theory
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• v.27 no.5
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• pp.529-539
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• 2000

This paper proposes a prefetch-based disk buffer management algorithm, which we call W2R (Veighingjwaiting Room). Instead of using elaborate prefetching schemes to decide which blockto prefetch and when, we simply follow the LRU-OBL (One Block Lookahead) approach and prefetchthe logical next block along with the block that is being referenced. The basic difference is that theW2R algorithm logically partitions the buffer into two rooms, namely, the Weighing Room and theWaiting Room. The referenced, hence fetched block is placed in the Weighing Room, while theprefetched logical next block is placed in the Waiting Room. By so doing, we alleviate some inherentdeficiencies of blindly prefetching the logical next block of a referenced block. Specifically, a prefetchedblock that is never used may replace a possibly valuable block and a prefetched block, thoughreferenced in the future, may replace a block that is used earlier than itself. We show through tracedriven simulation that for the workloads and the environments considered the W2R algorithm improvesthe hit rate by a maximum of 23.19 percentage points compared to the 2Q algorithm and a maximumof 10,25 percentage feints compared to the LRU-OBL algorithm.

• Journal of KIISE:Computing Practices and Letters
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• v.16 no.6
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• pp.673-677
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• 2010

Recently, NAND flash memory has been widely used in embedded systems, personal computers, and server systems because of its attractive features, such as non-volatility, fast access speed, shock resistance, and low power consumption. Due to its hardware characteristics, specifically its 'erase-before-write' feature, Flash Translation Layer is required for using flash memory like hard disk drive. Many FTL schemes have been proposed, but conventional FTL schemes have problems such as block thrashing and block associativity problem. The KAST scheme tried to solve these problems by limiting the number of associations between data block and log block to K. But it has also block thrashing problem in random access I/O pattern. In this paper, we proposed a new FTL scheme, UDA-LBAST. Like KAST, the proposed scheme also limits the log block association, but does not limit data block association. So we could minimize the cost of merge operations, and reduce merge costs by using a new block reclaim scheme, log block garbage collection.

• Journal of KIISE:Computing Practices and Letters
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• v.9 no.6
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• pp.635-645
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• 2003

One of very important features that are necessarily supported by clustered parallel computer systems is a single I/O system image in which users can access both the local and remote I/O resources transparently. In this paper, we propose an efficient disk sharing technique supporting a single disk I/O system image architecture. The design separates the I/O subsystem of a cluster into the file system and a set of virtual hard disk drivers. The virtual hard disk driver deals with a hard disk in the remote node as a local hard disk. All services provided by it are performed in the device driver level without any modification of file systems. Users can, therefore, access all the disks in the cluster regardless of their locations. Our virtual hard disk driver is implemented under the linux, and also tested in a linux cluster system. We find by experiments that it can successfully support a single disk I/O space, and at the same time it shows better performance than NFS. We are sure that this paper can be a guideline for single I/O space of other devices to be easily constructed.

• Journal of KIISE:Computing Practices and Letters
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• v.13 no.7
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• pp.508-519
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• 2007

Flash memory based storage has been used in various mobile systems and now is to be used in Laptop computers in the name of Solid State Disk. The Flash memory has not only merits in terms of weight, shock resistance, and power consumption but also limitations like erase-before-write property. To overcome these limitations, Flash memory based storage requires special address mapping software called FTL(Flash-memory Translation Layer), which often performs merge operation for block recycling. In order to reduce block recycling cost in NAND Flash memory based storage, we introduce another block recycling scheme which we call migration. As a result, the FTL can select either merge or migration depending on their costs for each block recycling. Experimental results with Postmark benchmark and embedded system workload show that this cost-based selection of migration/merge operation improves the performance of Flash memory based storage. Also, we present a solution of macroscopic optimal migration/merge sequence that minimizes a block recycling cost for each migration/merge combination period. Experimental results show that the performance of Flash memory based storage can be more improved by the macroscopic optimization than the simple cost-based selection.

• Journal of Korea Spatial Information System Society
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• v.10 no.2
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• pp.1-12
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• 2008

Automatic semiconductor manufacture system generating transaction from 50,000 to 500,000 per a second needs storage management system processing very large data at once. A lot of storage management systems are researched for storing very large data. Existing storage management system is typical DBMS on a disk. It is difficult that the DBMS on a disk processes the 500,000 number of insert transaction per a second. So, the DBMS on main memory appeared to use memory. But it is difficultthat very large data stores into the DBMS on a memory because of limited amount of memory. In this paper we propose storage management system using insert transaction of a block unit that can process insert transaction over 50,000 and store data on low storage cost. A transaction of a block unit can decrease cost for a log and index per each tuple as transforming a transaction of a tuple unit to a block unit. Besides, the proposed system come cost to decompress all block of data because the information of each field be loss. To solve the problems, the proposed system generates the index of each compressed block to prevent reducing speed for searching. The proposed system can store very large data generated in semiconductor system and reduce storage cost.

• Journal of KIISE:Computer Systems and Theory
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• v.27 no.3
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• pp.324-336
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• 2000

The paper proposes an efficient buffer management scheme to enhance performance of the disk I/O system. Without any user level information, the proposed scheme automatically detects the block reference patterns of applications by associating block attributes with forward distance of a block. Based on the detected patterns, the scheme applies an appropriate replacement policy to each application. We also present a new block allocation scheme to improve the performance of buffer cache when kernel needs to allocate a cache block due to a cache miss. The allocation scheme analyzes the cache hit ratio of each application based on block reference patterns and allocates a cache block to maximize cache hit ratios of system. These all procedures are performed on-line, as well as automatically at system level. We evaluate the scheme by trace-driven simulation. Experimental results show that our scheme leads to significant improvements in hit ratios of cache blocks compared to the traditional schemes and requires low overhead.

• Proceedings of the IEEK Conference
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• 2002.07b
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• pp.1296-1299
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• 2002

We implemented a CD signal processor operated on a CAV 48-speed CD-ROM drive into a VLSI. The CD signal processor is a mixed mode monolithic IC including servo-processor, data recovery, data-processor, and I-bit DAC. For servo signal processing, we included a DSP core, while, for CAV mode playback, we adopted a PLL with a wide recovery range. Data processor (DP) was designed to meet the yellow book specification.［2］So, the DP block consists of EFM demodulator, C1/C2 ECC block, audio processor and a block transferring data to an ATAPI chip. A modified Euclid's algorithm was used as a key equation solver for the ECC block To achieve the high-speed decoding, the RS decoder is operated by a pipelined method. Audio playability is increased by playing a CD-DA disc at the speed of 12X or 16X. For this, subcode sync and data are processed in the same way as main data processing. The overall performance of IC is verified by measuring a transfer rate from the innermost area of disc to the outermost area. At 48-speed, the operating frequency is 210 ㎒, and this chip is fabricated by 0.35 um STD90 cell library of Samsung Electronics.

• Journal of the Korean Society of Manufacturing Process Engineers
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• v.16 no.1
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• pp.149-156
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• 2017

Graphene nanoplatelet (GNP)-reinforced alumina ($Al_2O_3$) is a promising material for micro-partapplications, particularly micro-nozzle shapes, because of its excellent wearresistance. In this study, a $Al_2O_3$/GNPcomposite with 15 vol% graphene nanoplatelets (GNP) was highly densified and fabricated via spark plasma sintering for micro-electrical discharge drilling (Micro-ED drilling) and the wear resistance property of the composite is evaluated via the ball-on-disk method. In addition, the diameter and shape of the micro-electrodes machined by wire electrical discharge grinding (WEDG), block electrical discharge grinding (BEDG), and new linear block moving electrical discharge grinding (LBMEDG) methods are systematically compared and analyzed to observe the micro-hole machining in the micro-ED drilling of the $Al_2O_3$/15vol% GNP composite.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.5
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• pp.41-47
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• 2010

This paper has proposed parallel BCH, one of error correction coding methods which has been used to NAND flash memory for SSD(solid state disk). To alter error correction capability, the proposed design improved reliability on data block has higher error rate as used frequency increasingly. Decoding parallel process bit width is as two times as encoding parallel process bit width, that could reduce decoding processing time, accordingly resulting in one half reduction over conventional ECC.