• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.7
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• pp.29-38
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• 2009

In this paper, a high performance pipelined computing design of parallel multiplier-temporal buffer-parallel accumulator is present for the convolution-based non-cascaded architecture aiming at the real time Discrete Wavelet Transform(DWT) processing. The convolved multiplication of DWT would be reduced upto 1/4 by utilizing the filter coefficients symmetry and the up/down sampling; and it could be dealt with 3-5 times faster computation by LUT-based DA multiplication of multiple filter coefficients parallelized for product terms with an image data. Further, the reutilization of computed product terms could be achieved by storing in the temporal buffer, which yields the saving of computation as well as dynamic power by 50%. The convolved product terms of image data and filter coefficients are realigned and stored in the temporal buffer for the accumulated addition. Then, the buffer management of parallel aligned storage is carried out for the high speed sequential retrieval of parallel accumulations. The convolved computation is pipelined with parallel multiplier-temporal buffer-parallel accumulation in which the parallelization of temporal buffer and accumulator is optimize, with respect to the performance of parallel DA multiplier, to improve the pipelining performance. The proposed architecture is back-end designed with 0.18um library, which verifies the 30fps throughput of SVGA(800$\times$600) images at 90MHz.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.39 no.4
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• pp.429-441
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• 2002

This paper concerns extracting 3D motion information from a 3D input device in real time focused to enabling effective human-computer interaction. In particular, we develop a novel algorithm for extracting 6 degrees-of-freedom motion information from a 3D input device by employing an epipolar geometry of stereo camera, color, motion, and structure information, free from requiring the aid of camera calibration object. To extract 3D motion, we first determine the epipolar geometry of stereo camera by computing the perspective projection matrix and perspective distortion matrix. We then incorporate the proposed Motion Adaptive Weighted Unmatched Pixel Count algorithm performing color transformation, unmatched pixel counting, discrete Kalman filtering, and principal component analysis. The extracted 3D motion information can be applied to controlling virtual objects or aiding the navigation device that controls the viewpoint of a user in virtual reality setting. Since the stereo vision-based 3D input device is wireless, it provides users with a means for more natural and efficient interface, thus effectively realizing a feeling of immersion.

• International Journal of Automotive Technology
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• v.8 no.3
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• pp.259-268
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• 2007

A knock detection circuit that is based on the signal of an accelerometer installed on the engine block of a spark ignition automotive engine has a band-pass filter with a certain frequency as a parameter to be calibrated. A new statistical method for the determination of the frequency which is the most suitable for the knock detection in real-time applications is proposed. The method uses both the cylinder pressure and block vibration signals and is divided into two steps. In both steps, a new recursive trigonometric interpolation method that calculates the frequency contents of the signals is applied. The new trigonometric interpolation method developed in this paper improves the performance of the Discrete Fourier Transformation, allowing a flexible choice of the size of the moving window. In the first step, the frequency contents of the cylinder pressure signal are calculated. The knock is detected in the cylinder of the engine cycle for which at least one value of the maximal amplitudes calculated via the trigonometric interpolation method exceeds a threshold value indicating a considerable amount of oscillations in the pressure signal; this cycle is selected as a knocking cycle. In the second step, the frequency analysis is performed on the block vibration signal for the cycles selected in the previous step. The knock detectability, which is an individual cylinder attribute at a certain frequency, is verified via a statistical hypothesis test for testing the equality of two mean values, i.e. mean values of the amplitudes for knocking and non-knocking cycles. Signal-to-noise ratio is associated in this paper with the value of t-statistic. The frequency with the largest signal-to-noise ratio (the value of t-statistic) is chosen for implementation in the engine knock detection circuit.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.10
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• pp.148-158
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• 2012

This paper presents the design of the incremental delta-sigma ADC. The proposed circuit consists of pre-amplifier, S & H circuit, MUX, delta-sigma modulator, and decimation filter. Third-order discrete-time delta-sigma modulator with 1-bit quantization were fabricated by a $0.18{\mu}m$ CMOS technology. The designed circuit show that the modulator achieves 87.8 dB signal-to-noise and distortion ratio (SNDR) over a 5 kHz signal bandwidth and differential nonlinearity (DNL) of ${\pm}0.25$ LSB, integral nonlinearity (INL) of ${\pm}0.2$ LSB. Power consumption of delta-sigma modulator is $941.6{\mu}W$. It was decided that N cycles are 200 clock for 16-bits output.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.37 no.5C
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• pp.393-402
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• 2012

In this study, we propose a signal processing algorithm to measure the arousal level of a human subject using a PPG(Photoplethysmography) sensor. From the measured PPG signals, the arousal level is determined by PPI(Pulse to Pulse Interval) and discrete-time signal processing. We ran psychophysical experiments displaying visual stimuli on TV display while measuring PPG signal from a finger, where the nature landscape scenes were used for restorative effect, and the urban environments were used to stimulate the stress. However, the measured PPG signals may include noise due to subject movement and measurement error, which results in incorrect detections. In this paper, to mitigate the noise impact on stimulus detection, we propose a detecting algorithm using digital signal processing methods and statistics of measured signals. A filter is adopted to remove a high frequency noise and adaptively designed taking into account the statistics of the measured PPG signals. Moreover we employ a hysteresis method to reduce the distortion of PPI in decision of emotional. Via experiment, we show that the proposed scheme reduces signal noise and improves stimulus detection.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.4 s.334
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• pp.19-28
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• 2005

In this paper, we proposed a parallel fast 2-D discrete wavelet transform hardware architecture based on lifting scheme. The proposed architecture improved the 2-D processing speed, and reduced internal memory buffer size. The previous lifting scheme based parallel 2-D wavelet transform architectures were consisted with row direction and column direction modules, which were pair of prediction and update filter module. In 2-D wavelet transform, column direction processing used the row direction results, which were not generated in column direction order but in row direction order, so most hardware architecture need internal buffer memory. The proposed architecture focused on the reducing of the internal memory buffer size and the total calculation time. Reducing the total calculation time, we proposed a 4-way data flow scheduling and memory based parallel hardware architecture. The 4-way data flow scheduling can increase the row direction parallel performance, and reduced the initial latency of starting of the row direction calculation. In this hardware architecture, the internal buffer memory didn't used to store the results of the row direction calculation, while it contained intermediate values of column direction calculation. This method is very effective in column direction processing, because the input data of column direction were not generated in column direction order The proposed architecture was implemented with VHDL and Altera Stratix device. The implementation results showed overall calculation time reduced from $N^2/2+\alpha$ to $N^2/4+\beta$, and internal buffer memory size reduced by around $50\%$ of previous works.