• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.1C
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• pp.102-110
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• 2004

In this paper, we propose a VLSI structure of real-time image compression and reconstruction processor using 2-D discrete wavelet transform and implement into a hardware which use minimal hardware resource using ASIC library. In the implemented hardware, Data path part consists of the DWT kernel for the wavelet transform and inverse transform, quantizer/dequantizer, the huffman encoder/huffman decoder, the adder/buffer for the inverse wavelet transform, and the interface modules for input/output. Control part consists of the programming register, the controller which decodes the instructions and generates the control signals, and the status register for indicating the internal state into the external of circuit. According to the programming condition, the designed circuit has the various selective output formats which are wavelet coefficient, quantization coefficient or index, and Huffman code in image compression mode, and Huffman decoding result, reconstructed quantization coefficient, and reconstructed wavelet coefficient in image reconstructed mode. The programming register has 16 stages and one instruction can be used for a horizontal(or vertical) filtering in a level. Since each register automatically operated in the right order, 4-level discrete wavelet transform can be executed by a programming. We synthesized the designed circuit with synthesis library of Hynix 0.35um CMOS fabrication using the synthesis tool, Synopsys and extracted the gate-level netlist. From the netlist, timing information was extracted using Vela tool. We executed the timing simulation with the extracted netlist and timing information using NC-Verilog tool. Also PNR and layout process was executed using Apollo tool. The Implemented hardware has about 50,000 gate sizes and stably operates in 80MHz clock frequency.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.4B
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• pp.771-782
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• 2000

In this paper, an H.263 video codec is implemented by adopting the concept of hardware and software co-design. Each module of the codec is investigated to find which approach between hardware and software is better to achieve real-time processing speed as well as flexibility. The hardware portion includes motion-related engines, such as motion estimation and compensation, and a memory control part. The remaining portion of theH.263 video codec is implemented in software using a RISC processor. This paper also introduces efficient design methods for hardware and software modules. In hardware, an area-efficient architecture for the motion estimator of a multi-resolution block matching algorithm using multiple candidates and spatial correlation in motion vector fields (MRMCS), is suggested to reduce the chip size. Software optimization techniques are also explored by using the statistics of transformed coefficients and the minimum sum of absolute difference (SAD)obtained from the motion estimator.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.10
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• pp.6-14
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• 2011

This paper presents the design of the battery sensor IC for instrumentation of current, voltage using delta-sigma ADC. The proposed circuit consists of programmable gain instrumentation amplifier (PGIA) and second-order discrete-time delta-sigma modulator with 1-bit quantization were fabricated by a 0.25 ${\mu}m$ CMOS technology. Design circuit show that the modulator achieves 82 dB signal-to-noise ratio (SNR) over a 2 kHz signal bandwidth with an oversampling ratio (OSR) of 256 and differential nonlinearity (DNL) of ${\pm}$ 0.3 LSB, integral nonlinearity (INL) of ${\pm}$ 0.5 LSB. Power consumption is 4.5 mW.

• Nuclear Engineering and Technology
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• v.14 no.4
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• pp.196-203
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• 1982

To transport the spent fuel assemblies of Korea Nuclear Unit 1, which is a Westinghouse type two loop pressurized water reactor, it has been found that steel is the most appropriate material for the design of a shipping cask in comparison with lead and depleted uranium. The proposed shipping cask will transport nine fuel assemblies at the same time and is well within the weight limit of transportation by unrestricted rail car. The cask requires 33cm thick steel shield and 27cm thick water region to satisfy the 3 feet apart dose rate limit set forth in 10 CFR 71, and 1.27cm thick steel boron fuel basket to hold the fuel elements inside the cask and control the effective multiplication factor. As a safety analysis, the fuel cladding and centerline temperatures were calculated under the accident condition of complete loss of water coolant, and it was found that the temperature was much lower than the limit of the melting point. k$_{eff}$ was calculated with fresh fuel assemblies, which was found to be well lower than 0.95. For shielding computation, the multipurpose Monte Carlo code MORSE-CG and one dimensional discrete ordinates transport code ANISN were used, and the Monte Carlo codes KENO and MORSE-CG were used for criticality calculation. The radiation source terms were calculated using ORIGEN-79.9.

• Journal of the Korea Society for Simulation
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• v.22 no.1
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• pp.21-30
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• 2013

A hybrid system is a combination of sub systems which have different types of state and time: a typical example is a combination of discrete event and continuous systems. A HDEVS(Hybrid DEVS) formalism was proposed for modeling and analyzing a hybrid system. The HDEVS formalism allows modelers to construct a hierarchical and modular model based on the mathematical set theory. Because the HDEVS formalism was applied to the distributed and interoperated simulators, modelers should make several heterogenous models dividing a target system. Hence, this paper proposes an extended hybrid coupled model of HDEVS formalism and an integrated hybrid modeling methodology in contrast to the existing simulation framework on interoperable simulators. By applying the proposed modeling method, a target system can be translated to a hybrid model in a similar form as the target system. This paper also contains a simulation engine design for the proposed modeling methodlogy and a case study which simulates water tank control systems.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2022.05a
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• pp.147-149
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• 2022

This paper proposes a state machine design methodology in which an interactive robot that mimics discrete trial training (DTT protocol) can support social interaction training for children with autism. The robot applied to social interaction training uses the response to the provided training stimulus as a quantitative indicator by processing the data received from the sensors measuring the behavioral response of the child. In this process, the state machine is used as information that classifies the state of the acquired data and provides the subsequent stimulus for DTT protocol. Through the joint attentional training, it can be used as evidence-based treatment information by quantitatively classifying the data on the number of sustainable and DTT protocol and the child's response, as well as the current reaction status of the child to the observer performing remote monitoring. At the same time, it was confirmed that it is possible to properly respond to misrecognition situations.

• 제어로봇시스템학회:학술대회논문집
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• 1991.10b
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• pp.1659-1663
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• 1991

A new control design methodology is presented here which is based on a nonlinear time-series reference model. It is indicated by highly nonlinear simulations that such designs successfully stabilize troublesome aircraft maneuvers undergoing large changes in angle of attack as well as large electric power transients due to line faults. In both applications, the nonlinear controller was significantly better than the corresponding linear adaptive controller. For the electric power network, a flexible a.c. transmission system (FACTS) with series capacitor power feedback control is studied. A bilinear auto-regressive moving average (BARMA) reference model is identified from system data and the feedback control manipulated according to a desired reference state. The control is optimized according to a predictive one-step quadratic performance index (J). A similar algorithm is derived for control of rapid changes in aircraft angle of attack over a normally unstable flight regime. In the latter case, however, a generalization of a bilinear time-series model reference includes quadratic and cubic terms in angle of attack. These applications are typical of the numerous plants for which nonlinear adaptive control has the potential to provide significant performance improvements. For aircraft control, significant maneuverability gains can provide safer transportation under large windshear disturbances as well as tactical advantages. For FACTS, there is the potential for significant increase in admissible electric power transmission over available transmission lines along with energy conservation. Electric power systems are inherently nonlinear for significant transient variations from synchronism such as may result for large fault disturbances. In such cases, traditional linear controllers may not stabilize the swing (in rotor angle) without inefficient energy wasting strategies to shed loads, etc. Fortunately, the advent of power electronics (e.g., high-speed thyristors) admits the possibility of adaptive control by means of FACTS. Line admittance manipulation seems to be an effective means to achieve stabilization and high efficiency for such FACTS. This results in parametric (or multiplicative) control of a highly nonlinear plant.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.1
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• pp.49-58
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• 1999

This paper describes an integrated low pass filter fabricated by using $0.8{\mu}m$ single poly CMOS ASIC technology. The filter has been designed for a 5th-order elliptic switched capacitor filter with cutoff frequency of 5khz, 0.1dB passband ripple. The filter consists of MOS swiches poly capacitors and five CMOS op-amps. For the realization of the SC filter, continuous time transfer function H(s) is obtained from LC passive type, and transfered as discrete time transfer H(z) through bilinear-z transform. Another filter has been designed by capacitor scaling for reduced chip area, considering dynamic range of the op-amp. The test results of two fabricated filters are cutoff frequency of 4.96~4.98khz, 35~38dB gain attenuation and 0.72~0.81dB passband ripple with the ${\pm}2.5V$power supply clock of 50KHz.

• Journal of Advanced Navigation Technology
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• v.22 no.3
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• pp.228-232
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• 2018

Dealing with quntization error in a control system properly becomes much more important as many devices are connected through network and controlled. Thus, in this paper, we study a data rate condition on quantizer to achieve practical stability in a discrete time linear time invariant system with state feedback control. First, required data rate is shown to depend on eigenvalue of the closed loop system, the size of the initial state vector, the magnitude of initial quantization error, and control gain in the absence of process noise. It additionally depends on the maximum magnitude of process noise when noise is not zero. Asymptotic analysis shows that a new design method may be needed to reduce the date rate for a networked control in the presence of quantization error and noise.. We provide a simple numerical evaluation of uniform quantizer and logarithmic qunatizer to assess their characteristics of practical stability depending on data rate in the presence of noise.

• Journal of KIISE:Computing Practices and Letters
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• v.13 no.6
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• pp.358-370
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• 2007

Software simulations have been widely used for the design and application development of a wireless sensor network that is an infrastructure of ubiquitous computing. In this study, we develop a sensor network simulator that can verify the behavior of sensor network applications, estimate execution time and power consumption, and simulate a large-scale sensor network. To implement the simulator, we use an instruction-level parallel discrete-event simulation method. Instruction-level simulation uses executable images loaded into a real sensor board as workload, such that it results in the high degree of details. Parallel simulation makes simulation of a large-scale sensor network possible by distributing workload into multiple computers. The simulator can predict the amount of power consumption based on operating time of modules in a sensor node and counting the number of executed instructions by kind. Also it can simulate ubiquitous applications with various scenarios and debug programs. Instruction traces used as workload for simulations are executable images produced by the cross-compiler for ATmega128L microcontroller.