• Journal of Institute of Control, Robotics and Systems
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• v.7 no.4
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• pp.362-368
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• 2001

We study on the velocity matching algorithm for transfer alignment of inertial navigation system(INS) using a robust H$_2$ filter. We suggest an uncertainty model and a discrete robust H$_2$filter for INS and apply the suggested robust H$_2$ filter to the uncertainty model. The discrete robust H$_2$filter is shown by simulation to have better performance time and accuracy than Kalman filter.

• Proceedings of the KIEE Conference
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• 1990.07a
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• pp.60-63
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• 1990

This note presents a direct adaptive pole assignment control for general discrete, linear, time-invariant, nonmimum phase system.Controller parameters are estimated from the recursive least-squares algorithm, and some additional auxiliary parameters are obtained from aset of recursive equations based on a certain polynomial identity which is derived from the pole assignment equation and the Bezout identity. This scheme increase the numerical stability of the auxiliary parameters, and guarantees local convergence without any extra conditions for the external input. The effectiveness of the proposed scheme is demonstrated by the computer simulation.

• Proceedings of the KIEE Conference
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• 1990.07a
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• pp.43-46
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• 1990

A general scheme for a discrete adaptive observer having exponetial weighting properties is presented for a single-input single-output linear system. In this scheme, all the past measurement data are weighted esponetially both with the weighting factor and the stable matrix F. This observer is then implemented in the design of an indirect adaptive pole placement contoller. To increase nemerical stability in getting the controller parameter, a recusive algorithm is introduced. It is shown that the overall control scheme is globally stable with the persistent excition

• Proceedings of the KIEE Conference
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• 1990.07a
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• pp.64-67
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• 1990

A parallel processing algorithm for discrete Kalman filter, which is one of the most commonly used filtering technique in modern control, signal processing, and communication. is proposed. Previously proposed parallel algorithms to decrease the number of computations needed in the Kalman filter are the hierachical structures by distributed processing of measurements, or the systolic structures to disperse the computational burden. In this paper, a new parallel Kalman filter employing a structure similar to recursive doubling is proposed. Estimated values of state variables by the new algorithm converge with two times faster data processing speed than that of the conventional Kalman filter. Moreover it maintains the optimality of the conventional Kalman filter.

• Journal of Korean Society of Industrial and Systems Engineering
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• v.26 no.1
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• pp.79-84
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• 2003

종래의 연구들은 주로 시간이 경과함에 따라 수리비용과 고장시간 간격이 고정된 상태에서 최적교환시각(T)을 구하는 조건을 발견하는데 중점을 두었으나, 대부분의 시스템은 시간이 경과할수록 고장시간간격이 좁아지고 수리비용은 증가하는 것이 일반적이다. 본 논문에서는 위의 두 조건을 만족하는 보다 현실적인 모델을 구축하였으며, 또 일정시간 내에 2개의 시스템이 존재할 때 어느 조건 하에서 시스템이 확률적으로 우월한가를 분석하는 연구를 수행하였다. 즉, 시스템은 시간이 경과함에 따라 확률 P［N=k］로서 완전수리를, 1-P［N=k］로서 소수리를 행하는 모델을 고려하였다. 여기서 N은 연속된 완전수리 사이의 소수리의 수를 나타낸다. 또한 초기고장에 있어서 수리에 의해 새로운 시스템이 되는 확률이 높고, 고장횟수가 증가함에 따라 완전수리가 행해지는 확률이 낮아지는, 보다 현실에 가까운 모델을 구축하였다. 모델을 일반화하기 위해 수리비용은 확률변수로 가정하였다.

• Journal of Integrative Natural Science
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• v.13 no.2
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• pp.69-75
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• 2020

Multiple Input Multiple Output (MIMO) is one of the important wireless communication technologies. This paper proposes MIMO system capacity enhancement by using convolution of periodic circulating vector signals. This signal represents statistical dependencies between transmission signal with discrete noise and receiver signal with the linear shifting of MIMO channel capacity by positive extents. We examine the channel capacity, outage probability and SNR of MIMO receiver by adding log determinant signal with validated in terms of numerical simulation.

• Journal of Institute of Control, Robotics and Systems
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• v.6 no.9
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• pp.752-757
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• 2000

This paper considers a decentralized control problem of dicrete LTI systems which have time delay between interconnections. This paper provides sufficient conditions for the decentralized controller to exist as a H$\infty$ disturbance attenuation ${\gamma}$ of a scaled system and shows that the controller can be designed by using the discrete standard $H_{\infty}$ control theory.

• Journal of Institute of Control, Robotics and Systems
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• v.17 no.10
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• pp.960-966
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• 2011

In this paper, an $\mathfrak{H}$_/$\mathfrak{H}_{\infty}$ fault detection and isolation (FDI) observer design problem is investigated for discrete-time delayed systems. To that end, a bank consisting of the sensor's number of observers is introduced. Each residual should be sensitive to a certain partial group of faults, but robust against the disturbance as far as possible. We formulate this multiobjective FDI problem as $\mathfrak{H}$_/$\mathfrak{H}_{\infty}$ observers design problem. Sufficient design condition is expressed as iterative linear matrix inequalities. The fault is then detected and isolated by evaluating the residuals through an FDI decision logic. A computer simulation is provided for verification of the proposed technique.

• Proceedings of the IEEK Conference
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• summer
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• pp.15-18
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• 2004

In this paper we present a linear discrete bit-loading algorithm that maximizes the transmit bit rate using the channel informations to optimize the performance of the very high-speed digital subscriber line(VDSL) system. It will be useful under the constraint of a maximum transmit power for each user. When the level of crosstalk is high, the power allocation of a user changes the noise experienced by the other users in the same binder. In this case, the performance of DSL modems can be improved by jointly considering the bit and power allocation of all users.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.527-528
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• 2006

In this paper, we propose an IP design and implementation of System on a chip(SoC) for Discrete Cosine Transform (DCT) and Discrete Wavelet Transform (DWT) processor using adder-based DA(Adder-based Distributed Arithmetic). To reduced hardware cost and to improve operating speed, the combined DCT/ DWT processor used the bit-serial method and DA module. The transform of coefficient equation result in reduction in hardware cost and has a regularity in implementation. We use Verilog-HDL and Xilinx ISE for simulation and implement FPGA on SoCMaster-3.