• Journal of electromagnetic engineering and science
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• v.8 no.3
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• pp.114-118
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• 2008

Direct-conversion RF front-end for 5-GHz WLAN is implemented in $0.18-{\mu}m$ CMOS technology. The front-end consists of a low noise amplifier, and low flicker noise down-conversion mixers. For the mixer, an inductor is included to resonate out parasitic tail capacitances in the transconductance stage at the operating frequency, thereby improves the flicker noise performance of the mixer, and the overall noise performance of the front-end. The receiver RF front-end has 6.5 dB noise figure, - 13 dBm input IP3, and voltage conversion gain of 20 dB with the power consumption of 30 mW.

• 한국정보통신설비학회:학술대회논문집
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• 2009.08a
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• pp.305-308
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• 2009

This paper presents the design and analysis of RF Front End for Wireless Heartbeat measurement System. In this work LNA, an inductor connected at the gate of the cascode transistor and capacitive cross-coupling are strategically combined to reduce the noise and the nonlinearity influences of the cascode transistors in a differential LNA. The Mixer is implemented by using the Gilbert-type configuration, cross pmos injection technique and the resonating technique for the tail capacitance. The resulting LNA achieves 1.26 dB NF, better than 1.88dB NF Typical Also Mixer resulting achieves 9.8dB at 100KHz.

• Journal of electromagnetic engineering and science
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• v.2 no.2
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• pp.117-123
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• 2002

This paper describes the design for the resistive FET mixer with low If for the 4-Ch DBF(Digital Beam Forming) receiver This DBF receiver based on the direct conversion method is generally suitable for high-speed wireless mobile communications. A radio frequency(RF), a local oscillator(LO) and an intermediate frequency(If) considered in this research are 2.09 GHz, 2.08 CHz and 10 MHz, respectively. This mixer is composed of band pass filter, a low pass filter and a DC bias circuit. Super low noise HJ FET of NE3210S01 is considered in design. The RE input power, LO input power and Vcs are used -10 dBm, 6 dBm and -0.4 V, respectively. In the 4-Ch resistive FET mixer, the measured If and harmonic components of 10 MHe, 20 MHz and 2.087 CHz are about -19.2 dBm, -66 dBm and -48 dBm, respectively The If output power observed at each channel of 10 MHz is about -19.2 dBm and it is higher 28.8 dBm than the maximum harmonic component of 2.087 CHz. Each If output spectrum of the 4-Ch is observed almost same value and it shows a good agreement with the prediction.

• Journal of IKEEE
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• v.3 no.1 s.4
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• pp.69-78
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• 1999

In this paper, direct conversion receiver was designed to even harmonic anti-paralled diode pair ring mixer. Using a second harmonic component of LO instead of LO signal and RF signal are mixed by SHP(Sub Harmonic Pumped) mixer with anti-parallel diode pair. Canceling the harmonics of LO signal in ring mixer, SHP mixer using anti-parallel diode pair could mostly reduce the radiation of LO signal through a input port the most, good isolation characteristic, and low spurious characteristic by LO signal was shown over broad band. The produced SHP mixer showed LO/IF, RF/IF and LO/RF isolation was 24.6dB,36.2dB and 22.5dB respectively. And conversion loss was measured 15.6dB, IF output -35.6dBm with -20dBm RF input and 5.5dBm LO signal. 1dB compression point of If signal, in respect to RF signal, was found at the 0dbm RF signal.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.17 no.12 s.115
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• pp.1156-1163
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• 2006

This paper presents an ultra wideband(UWB) direct conversion mixer for IEEE 802.15.3a applications with simulation and measurement results. Since the direct conversion mixing causes dc-offset and even-order distortion, the proposed mixer adopts an anti-parallel diode pairs(APDPs) to solve these problems. The proposed mixer consists of an in-phase wilkinson power divider over $3.1{\sim}4.8GHz$, a wideband $45^{\circ}$ power divider over $1.5{\sim}2.4GHz$, and miniatured band pass filters(BPFs) for RF-LO isolations. The conversion loss is optimized with impedance matchings between APDPs and wideband components. The measured mixer shows the conversion loss of 13.5 dB, input third-order intercept-point($IIP_3$) of 7 dBm, and 1-dB gam compression point($P_{1dB}$) of -4 dBm. Quadrature(I/Q) outputs have the magnitude difference of about 1 dB and phase difference of ${\pm}3^{\circ}$.

• International Journal of Internet, Broadcasting and Communication
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• v.15 no.3
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• pp.122-128
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• 2023

This paper proposes two kinds of single-balanced direct conversion quadrature receivers using selfoscillating LMVs in which the voltage-controlled oscillator (VCO) itself operates as a mixer while generating an oscillation. The two LMVs are complementary coupled and series coupled to generate the quadrature oscillating signals, respectively. Using a 65 nm CMOS technology, the proposed quadrature receivers are designed and simulated. Oscillating at around 2.4 GHz frequency, the complementary coupled quadrature receiver achieves the phase noise of -28 dBc/Hz at 1KHz offset and -109 dBc/Hz at 1 MHz offset frequency. The other series coupled receiver achieves the phase noise of -31 dBc/Hz at 1KHz offset and -109 dBc/Hz at 1 MHz offset frequency. The simulated voltage conversion gain of the two single-balanced receivers is 37 dB and 45 dB, respectively. The double-sideband noise figure of the two receivers is 5.3 dB at 1 MHz offset. The quadrature receivers consume about 440 μW dc power from a 1.0-V supply.

• International journal of advanced smart convergence
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• v.10 no.3
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• pp.81-88
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• 2021

This paper proposes two types of subharmonic RF receiver front-end (called LMV) where, in a single stage, quadrature voltage-controlled oscillator (QVCO) is stacked on top of a low noise amplifier. Since the QVCO itself plays the role of the single-balanced subharmonic mixer with the dc current reuse technique by stacking, the proposed topology can remove the RF mixer component in the RF front-end and thus reduce the chip size and the power consumption. Another advantage of the proposed topologies is that many challenges of the direct conversion receiver can be easily evaded with the subharmonic mixing in the QVCO itself. The intermediate frequency signal can be directly extracted at the center taps of the two inductors of the QVCO. Using a 65 nm complementary metal oxide semiconductor (CMOS) technology, the proposed subharmonic RF front-ends are designed. Oscillating at around 2.4 GHz band, the proposed subharmonic LMVs are compared in terms of phase noise, voltage conversion gain and double sideband noise figure. The subharmonic LMVs consume about 330 ㎼ dc power from a 1-V supply.

• Journal of electromagnetic engineering and science
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• v.4 no.4
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• pp.143-149
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• 2004

This paper describes characteristics of the single-balanced low IF resistive FET mixer for the digital beam forming(DBF) receiver. This DBF receiver based on the direct conversion method is designed with Low IF I and Q channel. A radio frequency(RF), a local oscillator(LO) and an intermediate frequency(IF) considered in this research are 1950 MHz, 1940 MHz and 10 MHz, respectively. Super low noise HJ FET of NE3210S01 is considered in design. The measured results of the proposed mixer are observed IF output power of -22.8 dBm without spurious signal at 10 MHz, conversion loss of -12.8 dB, isolation characteristics of -20 dB below, 1 dB gain compression point(PldB) of -3.9 dBm, input third order intercept point(IIP3) of 20 dBm, output third order intercept point(OIP3) of 4 dBm and dynamic range of 30 dBm. The proposed mixer has 1.0 dB higher IIP3 than previously published single-balanced resistive and GaAs FET mixers, and has 3.0 dB higher IIP3 and 4.3 dB higher PldB than CMOS mixers. This mixer was fabricated on 0.7874 mm thick microstrip $substrate(\varepsilon_r=2.5)$ and the total size is $123.1\;mm\times107.6\;mm$.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.16 no.7 s.98
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• pp.681-689
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• 2005

This paper presents an ultra wide band(UWB) mixer using anti-parallel diode pair(APDP) with simulation and measurement results. The proposed mixer adopts the even-harmonic direct conversion mixing, which consists of a couple of filter, in-phase wilkinson power divider, wideband $45^{\circ}$ power divider, and APDP. The m mixer is operating over 3.1 to 4.8 GHz and producing quadrature(I/Q) outputs with a conversion loss of 18 dB and input third order intercept point($IIP_3$) of 15 dBm. I/Q outputs also have difference of about 0.5 dB and phase difference of ${\times}3^{\circ}$ and $P_{1dB}$ of 2 dBm.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.10 no.4
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• pp.105-113
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• 2010

In this paper, a 1.485 Gbps video signal transmission system using the carrier frequency of 240 GHz band was designed and simulated. The sub-harmonic mixer based on Schottky barrier diode was simulated in the transmitter and receiver. Both of heterodyne and direct detection receivers were simulated for each performance analysis. The ASK modulation was used in the transmitter and the envelop detection method was used in the receiver. The transmitter simulation results showed that the RF output power was -11.4 dBm($73{\mu}W$), when the IF input power was -3 dBm(0.5 mW) at the LO power of 7 dBm(5 mW) in sub-harmonic mixer, which corresponds to SSB(Single Side Band) conversion loss of 8.4 dB. This value is similar to the conversion loss of 8.0 dB(SSB) of VDI's commercial model WR3.4SHM(220~325 GHz) at 240 GHz. The combined transmitter and receiver simulation results showed that the recovered signal waveforms were in good agreement to the transmitted 1.485 Gbps NRZ signal.