• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.9A
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• pp.728-735
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• 2003

It is a mainly issue that provide mobility smoothly in Mobile IP networks. The IP mobility support being standardized in the IETF utilized tunneling of IP packets from a home agent to foreign agent and utilized reverse tunneling of IP packets from foreign agent to home agent. In this paper, We propose that solve the triangular routing problem in IP mobility and that lessen the messages about IETF routing optimization. Through the Mobile Routing Table on the edge router, agent process the message instead of a end node when handoff occur and that lessen the routing path length by sending directly from FA to to Correspond Node's router. This action lessen the message occurrence frequency and the packet drop. We compare the standard IP, Routing Optimization of Mobile IP, Wu's method and the proposed algorithm. Finally, the simulation results are presented.

• Proceedings of the Korea Crystallographic Association Conference
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• 2002.11a
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• pp.42-43
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• 2002

반도체 디바이스의 발전은 높은 직접화 및 동작 속도를 추구하고 있으며, 이를 위해서 MOSFET의 scale down시 발생되는 문제를 해결해야만 한다. 특히, Channel이 짧아짐으로써 발생하는 device의 열화현상으로 동작전압의 조절이 어려워 짐을 해결해야만 하며, gate oxide 두께를 줄임으로써 억제할 수 있다고 알려져 왔다. 현재, gate oxide으로 사용되고 있는 SiO2박막은 비정질로써 ～8.7 eV의 높은 band gap과 Si기판 위에서 성장이 용이하며 안정하다는 장점이 있으나, 두께가 1.6 nm 이하로 얇아질 경우 전자의 direct Tunneling에 의한 leakage current 증가와 gate impurity인 Boron의 channel로의 확산, 그리고 poly Si gate의 depletion effect[1,2] 등의 문제점으로 더 이상 사용할 수 없게 된다. 2001년 ITRS에 의하면 ASIC제품의 경우 2004년부터 0.9～l.4 nm 이하의 EOT가 요구된다고 발표하였다. 따라서, gate oxide의 물리적인 두께를 증가시켜 전자의 Tunneling을 억제하는 동시에 유전막에 걸리는 capacitance를 크게 할 수 있다는 측면에서 high-k 재료를 적용하기 위한 연구가 진행되고 있다[3]. High-k 재료로 가능성 있는 절연체들로는 A1₂O₃, Y₂O₃, CeO₂, Ta₂O, TiO₂, HfO₂, ZrO₂,STO 그리고 BST등이 있으며, 이들 재료 중 gate oxide에 적용하기 위해 크게 두 가지 측면에서 고려해야 하는데, 첫째, Si과 열역학적으로 안정하여 후속 열처리 공정에서 계면층 형성을 배제하여야 하며 둘째, 일반적으로 high-k 재료들은 유전상수에 반비례하는 band gap을 갖는 것으로 알려줘 있는데 이 Barrier Height에 지수적으로 의존하는 leakage current때문에 절연체의 band gap이 낮아서는 안 된다는 점이다. 최근 20이상의 유전상수와 ～5 eV 이상의 Band Gap을 가지며 Si기판과 열역학적으로 안정한 ZrO₂[4], HfiO₂[5]가 관심을 끌고 있다. HfO₂은 ～30의 고유전상수, ～5.7 eV의 높은 band gap, 실리콘 기판과의 열역학적 안전성 그리고 poly-Si와 호환성등의 장점으로 최근 많이 연구가 진행되고 있다. 또한, Hf은 SiO₂를 환원시켜 HfO₂가 될 수 있으며, 다른 silicide와 다르게 Hf silicide는 쉽게 산화될 수 있는 점이 보고되고 있다.

• Current Photovoltaic Research
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• v.12 no.2
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• pp.31-36
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• 2024

Passivating contacts are a promising technology for achieving high efficiency Si solar cells by reducing direct metal/Si contact. Among them, a polysilicon (poly-Si) based passivating contact solar cells achieve high passivation quality through a tunnel oxide (SiO_x) and poly-Si. In poly-Si/SiO_x based solar cells, the passivation quality depends on the amount of dopant in-diffused into the bulk-Si. Therefore, our study fabricated cells by inserting silicon oxide (SiO₂) as a doping barrier before doping and analyzed the barrier effect of SiO₂. In the experiments, p⁺ poly-Si was formed using spin on dopant (SOD) method, and samples ware fabricated by controlling formation conditions such as existence of doping barrier and poly-Si thickness. Completed samples were measured using quasi steady state photoconductance (QSSPC). Based on these results, it was confirmed that possibility of achieving high V_oc by inserting a doping barrier even with thin poly-Si. In conclusion, an improvement in implied V_oc of up to approximately 20 mV was achieved compared to results with thicker poly-Si results.

• Journal of Electrochemical Science and Technology
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• v.14 no.1
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• pp.21-30
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• 2023

This work presents a correlation between the behavior of formic acid oxidation (FAO) on various Bi-modified Pt(poly) disk electrodes and their morphologies observed on Bi-modified Pt(111) disk electrodes using electrochemical scanning tunneling microscopy (EC-STM) to understand the effects of Bi on Pt. To distinguish the FAO activities of Bi on Pt and plain Pt around Bi, additional Pt was intentionally deposited using two different routes: direct route and iodine route. In direct route, Pt was directly deposited on Bi islands and plain Pt sites around Bi islands, while in iodine route, Pt was exclusively deposited on Bi islands by protecting plain Pt sites with adsorbed iodine. Thus, a comparison of FAO performances on the two Bi-modified Pt electrodes with additional Pt (deposited in the different ways) disclosed a difference in FAO performances on plain Pt sites and Bi islands. When Bi coverage was ~0.04, the Bi deposits were scattered Bi islands enhancing FAO on Pt(poly). The additional Pt deposits using direct route increased FAO efficiency, while the ones using iodine route slightly decreased FAO current. The EC-STM observations indicated that Pt deposits around Bi islands, not on Bi islands, were responsible for the FAO current increase on Bi-modified Pt(poly). The FAO efficiency on Bi-modified Pt(poly) with a Bi coverage of ~0.25 increased by a factor of 2. However, the additional Pt deposits using the two Pt deposition routes notably decreased the FAO current. The dependency of FAO on Bi coverage was discussed in terms of electronic effect and ensemble effect.

• JSTS:Journal of Semiconductor Technology and Science
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• v.1 no.2
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• pp.103-110
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• 2001

Gate oxide scaling for sub-l00nm CMOS devices has been studied. Issues on the gate oxide scaling are reviewed, which are boron penetration, reliability, and direct tunneling leakage currents. Reliability of Sub-2.0nm oxides and the device performance degradation due to boron penetration are investigated. Especially, the effect of gate leakage currents on the transistor characteristics is studied. As a result, it is proposed that thinner oxides than previous expectations may be usable as scaling proceeds. Based on the gate oxide thickness optimization process we have established, high performance CMOS transistors of $L_{gate}=70nm$ and $T_{ox}=1.4nm$ were fabricated, which showed excellent current drives of $860\mu\textrm{A}/\mu\textrm{m}$ (NMOS) and $350\mu\textrm{A}/\mu\textrm{m}$ (PMOS) at $I_{off}=10\mu\textrm{A}/\mu\textrm{m}$ and $V_dd=1.2V$, and CV/I of 1.60ps (NMOS) and 3.32ps(PMOS).

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.129-130
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• 2009

The P/E characteristics of $HfO_2$ CTF memory capacitor with $SiO_2/HfO_2/Al_2O_3$(OHA) engineered tunnel barrier were investigated. After a growth of thermal oxide with a thickness of 2 nm, 1 nm $HfO_2$ and 3 $Al_2O_3$ layers were deposited by atomic layer deposition (ALD) system. The band offset was calculated by analysis of conduction mechanisms through Fowler-Nordheim (FN) plot and Direct Tunneling (DT) plot. Moreover the PIE characteristics of $HfO_2$ CTF memory capacitor with OHA tunnel barrier was presented.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.5 no.7
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• pp.1257-1262
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• 2001

In recent years there has been a lot of interest in carrying IP over WDM networks in an efficient manner. The benefits here include larger bandwidth capacities, better network scalability, and more efficient operation. W based approach, termed "lambda-labeling" is presented for direct If over WDM integration. In this paper, we study on architecture approach method consider of optical Internet evolution that based on MPLamdaS conception of IETF. Label stack conception collect electronic LSP of optical LSP. This paper is proposed method of co-operation between MPLS domain and MPLambdaS domain. Additionally, proposed architecture of Edge Optical LSR.tical LSR.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.11a
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• pp.262-263
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• 2008

The Metal-Insulator-Silicon (MIS) capacitors with $SiO_2$ and high-k dielectric were investigated. The high-k dielectrics were obtained by atomic layer deposit (ALD) system. The electrical characteristics were investigated by measuring the current-voltage (I-V) characteristics. The conduction mechanisms were analyzed by using the Fowler-Nordheim (FN) plot and Direct Tunneling (DT) plot. As a result, the MIS capacitors with high-k dielectrics have lower leakage current densities than conventional tunnel-barrier with $SiO_2$ dielectrics.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.743-746
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• 2003

We have successfully used hydrophobic direct-wafer bonding, along with H-induced layer splitting of Ge, to transfer 700nm think, single-crystal Ge films to Si substrates. Optical and electrical properties have been also observed on these samples. Triple-junction solar cell structures gown on these Ge/Si heterostructure templates show comparable photoluminescence intensity and minority carrier lifetime to a control structure grown on bulk Ge. When heavily doped p$^{+}$Ge/p$^{+}$Si wafer bonded heterostructures were bonded, ohmic interfacial properties with less than 0.3Ω$\textrm{cm}^2$ specific resistance were observed indicating low loss thermal emission and tunneling processes over and through the potential barrier. Current-voltage (I-V) characteristics in p$^{+}$Ge/pSi structures show rectifying properties for room temperature bonded structures. After annealing at 40$0^{\circ}C$, the potential barrier was reduced and the barrier height no longer blocks current flow under bias. From these observations, interfacial atomic bonding structures of hydrophobically wafer bonded Ge/Si heterostructures are suggested.ested.

• JSTS:Journal of Semiconductor Technology and Science
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• v.3 no.2
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• pp.96-101
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• 2003

Direct evidence on the incorporation of high concentration of oxygen into undoped AlGaN layers for the AlGaN/GaN heterostuctures is provided by scanning photoemission microscopy using synchrotron radiation. In-situ annealing at $1000^{\circ}C$ resulted in a significant increase in the oxygen concentration at the AlGaN surface due to the predominant formation of Al-O bonds. The oxygen incorporation into the AlGaN layers resulting from the high reactivity of Al to oxygen can enhance the tunneling-assisted transport of electrons at the metal/AlGaN interface, leading to the reduction of the Schottky barrier height and the increase of the sheet carrier concentration near the AlGaN/GaN interface.