• Journal of Electrical Engineering and Technology
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• v.13 no.1
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• pp.362-371
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• 2018

This work proposes FPGA implementation of Carrier Disposition PWM for closed loop seven level diode clamped multilevel inverter in speed control of induction motor. VLSI architecture for carrier Disposition have been introduced through which PWM signals are fed to the neutral point seven level diode clamped multilevel using which the speed of the induction motor is controlled. This proposed VLSI architecture makes the power circuit to work better with reduced stresses across the switches and a very low voltage and current total harmonic distortion (THD). The output voltages, currents, torque & speed characteristics for seven level neutral point diode clamped multilevel inverter for AC drive was studied. It has observed the proposed scheme introduces less distortion and harmonics. The results were validated using real time results.

• Journal of Power Electronics
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• v.19 no.3
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• pp.702-713
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• 2019

Multilevel Inverters (MLIs) are widely used in medium voltage applications due to their various advantages. In addition, there are numerous types of MLIs for such applications. However, the diode-less 3-level (3L) T-type Neutral Point Clamped (NPC) MLI is the most advantageous due to its low conduction losses and high potential efficiency. The power circuit of a 3L T-type NPC is derived by the conventional two level inverter by a slight modification. In order to explore the MLI performance for various Pulse Width Modulation (PWM) schemes, this paper examines the operation of a 3L (five level line to line) T-type NPC MLI for various types of Multi-Carriers Pulse Width Modulation (MCPWM) schemes. These PWM schemes are compared in terms of their voltage profile, total harmonic distortion (THD) and conduction losses. In addition, a 3L T-type NPC MLI is also compared with the conventional NPC in terms of number of switches, clamping diodes, main diodes and capacitors. Moreover, the capacitor-balancing problem is also investigated using the Neutral Point Fluctuation (NPF) method with all of the MCPWM schemes. A 1kW 3L T-type NPC MLI is simulated in MATLAB/Simulink and implemented experimentally and its performance is tested with a 1HP induction motor. The results indicate that the 3L T-type NPC MLI has better performance than conventional NPC MLIs.

• Journal of Power Electronics
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• v.18 no.4
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• pp.1027-1036
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• 2018

In this paper a new generalized space vector pulse width modulation scheme is proposed based on the principle of reverse mapping to drive the switches of multilevel inverters. This projected scheme is developed based on the middle vector of the subhexagon which holds the tip of the reference vector, which plays a major role in mapping the reference vector. A new approach is offered to produce middle vector of the subhexagon which holds tip of the reference vector in the multilevel space vector plane. By using middle vector of the subhexagon, reference vector is linked towards the inner two level sub-hexagon. Then switching vectors, switching sequence and dwell times corresponding to a particular sector of a two-level inverter are determined. After that, by using the two level stage findings, the switching vectors related to exact position of the reference vector are directly generated based on principle of the reverse mapping approach and do not need to be found at n level stage. In the reverse mapping principle, the middle vector of subhexagon is added to the formerly found two level switching vectors. The proposed generalized algorithm is efficient and it can be applied to an inverter of any level. In this paper, the proposed scheme is explained for a five-level inverter and the performance is analyzed for five level and three level inverters through MATLAB. The simulation results are validated by implementing the propose scheme on a V/f controlled three-level inverter fed induction motor using dSPACE control desk.