• Proceedings of the KIEE Conference
• /
• 2002.11c
• /
• pp.197-200
• /
• 2002

We newly developed the procedures of X-ray Cargo inspection system with acquisition of multi-channel data, analog to digital converter and post logic circuit which is controlled by the FPGA. The IEEE1149.1 standard defines a four-wire serial interface(a fifth wire is optional)to access complex integrated circuits(ICs) such as PLD. This paper describes that Boundary_Scan test method applied to our home made cargo inspection system.

• Journal of the Semiconductor & Display Technology
• /
• v.15 no.2
• /
• pp.55-60
• /
• 2016

This study was developed through the secondary battery module charging/discharger possible utilization in the production process equipment circuit. The developed module is ensuring construction of efficient and productive charging and discharger through this research a limit on the yield and the price of existing single -channel charge and discharger circuit as a 5V 70A grade secondary battery Formation charge and discharger for up to 1 board 4 channels. In order to improve the sensing accuracy, through a robust differential amplifier circuit described using 16bit Analog-Digital Converter and noise was secured 16bit resolution sensing. The configuration also made demands for property Rise / Fall Time. Data Acquisition, discharge efficiency and also to fit the sink circuit temperature level for mass production.

• Proceedings of the KIPE Conference
• /
• 2005.07a
• /
• pp.487-489
• /
• 2005

This paper presents a wavelet-based neural network technology for the detection and classification of the short durations type of power quality disturbances. Transients happen during very short durations to the nano- and microsecond. Thus, a method for detecting and classifying transient signals at the same time and In an automatic combines the properties of the wavelet transform and the advantages of neural networks. Especially, the additional feature extraction to improve the recognition rate is considered. The configuration of the hardware of TMS320C6711 DSP based with 16 channel 20Mhz sampling rate A/D(Analog to Digital) converter and some case studies are described.

• Journal of IKEEE
• /
• v.13 no.4
• /
• pp.9-14
• /
• 2009

This paper describes measurement of an on-ship power supply noise in mixed-signal integrated circuits. To measure the on-chip power supply noise, we can check the effects of analog circuits and compensate it. This circuit consists of two independent measurement channels, each consisting of a sample and hold circuit and a frequency to digital converter which has a buffer and voltage controlled oscillator(VCO). The time-based voltage information and frequency-based power spectrum density(PSD) can be achieved by a simple analog to digital conversion scheme. The buffer works like a unit-gain buffer with a wide bandwidth and VCO has a high gain to improve resolution. This circuit was fabricated in a 0.18um CMOS technology and has 2.06mV/count. The noise measurement circuit consumes 15mW and occupies $0.768mm^2$.

• Journal of the Korean Society of Fisheries and Ocean Technology
• /
• v.35 no.3
• /
• pp.328-334
• /
• 1999

A fish pump makes very important roles in an automation system of an aquaculture farm, thus it has been used widely in order to transfer fishes from one place to the other place automatically. In spite of its significant roles, the efforts for developing performance and promoting efficiency of the fish pump are not sufficient yet. In this paper, a method which makes the fish pump automation system is suggested. Automation of the fish pump can be accomplished by using variable voltage and variable frequency inverter system including induction motors. Especially, very simple logic to generate Pulse width Modulation(PWM) wave to control induction motor efficiently and three steps speed control method to regulate liquid quantity of the fish pump simply are suggested. Owing to the simplifies speed control and PWM wave generation technique, a cheaper microprocessor, 80C196KC, than a digital signal Processor(DSP) can be used to operate control algorithm in induction motor systems for real time control Also, a new idea of remote control for the simplifies novel inverter system by Programmable logic Controller(PLC) without special output unit, digital to analog converter(D/A), is suggested in this paper. Consequently the function of reliability, availability and serviceability of the fish pump system are developed. It will be expected to contribute expanding of application of the fish pump in aquaculture farms because the system can reduce energy consumption and some difficulties according to manual operation prominently.

• Journal of information and communication convergence engineering
• /
• v.13 no.4
• /
• pp.235-240
• /
• 2015

A decimation chain for multi-standard reconfigurable radios is presented for 900-MHz and 1,900-MHz dual-band cellular standards with a data interpolator based on the Lagrange method for adjusting the variable data rate to a fixed data rate appropriate for each standard. The two proposed configurations are analyzed and compared to provide insight into aliasing and the signal bandwidth by means of a newly introduced measure called interpolation error. The average interpolation error is reduced as the ratio of the sampling frequency to the signal BW is increased. The decimation chain and the multi-rate analog-to-digital converter are simulated to compute the interpolation error and the output signal-to-noise ratio. Further, a method to operate the above-mentioned chain under a compressed mode of operation is proposed in order to guarantee continuous packet connectivity for inter-radio-access technologies. The presented decimation chain can be applied to LTE, WCDMA, GSM multi-mode multi-band digital front-end which will ultimately lead to the software-defined radio.

• Journal of the Institute of Electronics Engineers of Korea SC
• /
• v.37 no.6
• /
• pp.35-41
• /
• 2000

This paper describes a merged-capacitor switching (MCS) technique to improve the signal Processing speed and resolution of CMOS analog-to-digital converters (ADCs). The proposed MCS technique improves a sampling rate by reducing the number of capacitors used in conventional pipelined ADCs. The ADC capacitor mismatch can be minimized without additional power consumption, die area, and the loss of sampling rate, when the size of each unit capacitor is increased as much as the number of capacitors reduced by the MCS technique. It is verified that the ADC resolution based on the proposed MCS technique is extended further by employing a conventional commutated feedback-capacitor switching (CFCS) technique.

• Proceedings of the IEEK Conference
• /
• 2001.09a
• /
• pp.583-586
• /
• 2001

본 논문에서는 다중 대역통과 표본화 이론에 기반하여 1.9GHz IS-95신호와 2.2GHz IMT-2000 신호를 하나의 ADC(analog to digital converter)를 사용하여 동시에 표본화하고 디지털 처리를 수행하는 방법을 제안하고 실험을 통하여 검증하였다. 일반적인 방법으로는 본 논문에서 고려하는 두 신호를 동시에 표본화하기 위해서는 표본화 주파수가 최소한 1GHz 이상의 고속의 ADC를 사용해야 한다. 그러나 현재 ADC의 기술은 광대역의 신호를 직접 더지털화하기에는 아직 미흡하다. 반면에 대역통과 표본화 이론은 기존의 상용 ADC와 기콘의 RF 시스템을 이용하여 다른 대역에 위치한 두 신호를 통합처리 할 수 있는 기반을 제공하고 있다. 본 논문에서는 이러한 대역통과 표본화 이론에 기반을 두고 상용 ADC를 사용하여 표본화 시스템을 구현하여 IS-95신호와 IMT-2000 신호를 표본화하고 이를 컴퓨터에서 디지털 필터를 이용하여 두 신호를 분리하는 실험을 통하여 다중 대역통과 표본화의 적용 가능성을 검증하였다.

• The Transactions of The Korean Institute of Electrical Engineers
• /
• v.58 no.3
• /
• pp.627-631
• /
• 2009

This paper presents a novel current steering cell matrix DAC(digital-to-analog converter) architecture to reduce decoder area. The current cell matrix of a existing architecture is selected by columns and lows thermometer code decoder of input bits. But The current cell matrix of a proposal architecture is divided 2n by the thermometer code decoder of upper input bits and are selected by the thermometer code decoder of middle and lower input bits. Because of this configuration, decoder numbers have increased. But the gate number that composed of decoder has decreased. In case of the designed 8 bit current steering cell matrix DAC, the gate number of decoder has decreased by about 55% in comparison with a existing architecture.

• Proceedings of the IEEK Conference
• /
• 1998.06a
• /
• pp.518-521
• /
• 1998

This paper describes a 3.3V-65MHz 12BIT CMOS current-mode DAC designed with a 8 MSB current matirx stage and a 4 LSB binary weighting stage. The linearity errors caused by a voltage drop of the ground line and a threshold voltage mismatch of transistors have been reduced by the symmetrical routing method with ground line and the tree structure bias circuit, respectively. In order to realize a low glitch energy, a cascode current switch ahs been employed. The simulation results of the designed DAC show a coversion rate of 65MHz, a powr dissipation of 71.7mW, a DNL of .+-.0.2LSB and an INL of .+-.0.8LSB with a single powr supply of 3.3V for a CMOS 0.6.mu.m n-well technology.