• Journal of IKEEE
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• v.23 no.1
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• pp.35-43
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• 2019

A capacitor self-calibration is proposed to improve the linearity of the capacitor digital-to-analog converter (CDAC) for an asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) with 10-bit resolution. The proposed capacitor self-calibration is performed so that the value of each capacitor of the upper 5 bits of the 10-bit CDAC is equal to the sum of the values of the lower capacitors. According to the behavioral simulation results, the proposed capacitor self-calibration improves the performances of differential nonlinearity (DNL) and integral nonlinearity (INL) from -0.810/+0.194 LSBs and -0.832/+0.832 LSBs to -0.235/+0.178 LSBs and -0.227/+0.227 LSBs, respectively, when the maximum capacitor mismatch of the CDAC is 4%. The proposed 10-bit 20-MS/s asynchronous SAR ADC is implemented using a 110-nm CMOS process with supply of 1.2 V. The area and power consumption of the proposed asynchronous SAR ADC are $0.205mm^2$ and 1.25 mW, respectively. The proposed asynchronous SAR ADC with the capacitor calibration has a effective number of bits (ENOBs) of 9.194 bits at a sampling rate of 20 MS/s about a $2.4-V_{PP}$ differential analog input with a frequency of 96.13 kHz.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.16 no.2
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• pp.151-155
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• 2016

In this paper, we present the LED dimming control system by using ADPCM (Adaptive Differential Pulse Code Modulation). This ADPCM apparatus accurately controls the LED current with high resolution reducing the RFI (radio frequency interference) due to the spreading out of the harmonics of current of pulses. Additionally, this makes it easier to increase the accuracy of control operation. This study introduces to make a digitally controlled circuit for controlling LED with high-energy efficient by adopting pulse current to LED. The LED current drive system we designed are two systems, the digitally-controlled unit and analog switching mode power supply unit, can be developed separately. The simulation shows the sigma delta modulation of digital to analog converter's output when the input level is 0.7. From this simulation, the output is approached to accurately 0.15% to target value with 510 pulses.

• Journal of Advanced Navigation Technology
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• v.16 no.2
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• pp.351-359
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• 2012

This paper deals with the design and development of the remote control and measurement systems using CDMA(Code Division Multiple Access) data modem. We propose a bi-directional data communication link without the public IP address in CDMA modem device by the TCP/IP packet and SMS(Short Message Service) communication. The remote control and measurement systems are implemented by a Telit WM-800 modem as DCE(Data Communication Equipment), and Atmel AT89C51 microcontroller as DTE(Data Terminal Equipment). The user application software for the control and measurement system user, and the firmware software of device drivers for peripherals such as a digital input/output device, AD/DAC(Analog to Digital/Digital to Analog Converter), LCD, and temperature/humidity sensor are written in Microsoft C and Keil C language respectively for further various applications. The experimental result of the proposed control and measurement systems implemented in this paper is evaluated via real-time experiments, which works well as designed.

• The Transactions of the Korea Information Processing Society
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• v.1 no.4
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• pp.469-478
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• 1994

In this paper, a high speed, high resolution information processing digital- analog converter was designed for high definition color graphic, digital image signal processing, HDTV. For high speed operation, matrix type current cell array, latch which is not use pipelined, and two dimensional structure decoder using transmission gate were designed. It is adopted to fast-conversion, low-power implementation and exhibited high performance at linearity and accuracy. To reduce silicon area and to maintain resolution, current cell array composed of weighted and non-weighted current cells. In this paper, deglitching current cell design for high accuracy, new switching algorithm assert to reduce switching error. It's This circuit dissipates 130W with a 5-V power supply, and operate above 100MHz with 10 bit resolution.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.11
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• pp.83-94
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• 2003

In this paper. a highly linear and low glitch CMOS current mode digital-to-analog converter (DAC) by self calibration bias circuit is proposed. The architecture of the DAC is based on a current steering 6＋4 segmented type and new switching scheme for the current cell matrix, which reduced non-linearity error and graded error. In order to achieve a high performance DAC . novel current cell with a low spurious deglitching circuit and a new inverse thermometer decoder are proposed. The prototype DAC was implemented in a 0.35${\mu}{\textrm}{m}$ n-well CMOS technology. Experimental result show that SFDR is 60 ㏈ when sampling frequency is 32MHz and DAC output frequency is 7.92MHz. The DAC dissipates 46 mW at a 3.3 Volt single power supply and occupies a chip area of 1350${\mu}{\textrm}{m}$ ${\times}$750${\mu}{\textrm}{m}$.

• Journal of Sensor Science and Technology
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• v.26 no.5
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• pp.331-337
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• 2017

A readout circuit for a tactile sensor pad based on force sensing resistors was proposed, which was composed of an analog signal conditioning circuit and a digital circuit with a microcontroller. The conventional signal conditioning circuit has a dc offset voltage in the output signal, which results from the reference voltage applied to the FSR devices. The offset voltage reduces the dynamic range of the circuit and makes it difficult to operate the circuit under a low voltage power supply. In the proposed signal conditioning circuit, the dc offset voltage was removed completely. The microcontroller with A/D converter and D/A converter was used to enlarge the measurement range of pressure. For this, the microcontroller adjusts the FSR reference voltage according to the resistance magnitude of FSR under pressure. The operation of the proposed readout circuit which was connected to a tactile sensor pad with $5{\times}10$ FSR array was verified experimentally. The experimental results show the proposed readout circuit has the wider measurement range of pressure than the conventional circuit. The proposed circuit is suitable for low voltage and low power applications.

• 전기의세계
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• v.22 no.1
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• pp.35-41
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• 1973

An automatic point traffic control method is recommended for more idealistic traffic flow over coarse road netowrks. The automatic control apparatus recommended, consists of a transceiver, amplifier, digital-to-analog converter, signal light controller for emergency and steady state, and digital counter as monitor. The transmitter sends a signal to the target vy means of Microwave-FM-CW and a diode detector picks up the echo signal. Thus the operation of the entire system will be carried out through an open loop state. Some factors necessary for an ideal detector system are rapid response, longevity and stability. An analytical method of the Doppler effect substitutes the conventional frequency deviation into the amplitude of detector output. The changing rate of amplitude is proportional to the voltage of the detector output. Some induced formula from Maxwell's radiation field theory ensures this new method, and, new method, and proves the fact with an experimental data presentation. Stability depends upon Klystron as an oscillator and a diode as a detector. the transceiver installation affects on the response and sensitivity of the system. In accordance with the detector output, several targets are easily classified by amplitudes on the scope. The traffic flow, i.e., target movement which is analyzed by the amplitude method, is shown through the scope and indicates it on the digital counter. The best efficiency for the amplitude analysis can be attained through use of an antenna having the highest sensitivity.

• Journal of the Institute of Convergence Signal Processing
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• v.12 no.2
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• pp.139-144
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• 2011

The modern digital logic technology does not yet satisfy the speed requirements of real-time DSP circuits due to synchronized operation of multiplication and accumulation. This operation degrades DSP performance. Therefore, the double-base number system (DBNS) has emerged in DSP system as an alternative methodology because of fast multiplication and hardware simplicity. In this paper, authors propose a novel multiplication architecture. One operand is an output of a flash analog-to-digital converter (ADC) in DBNS format, while the other operand is a coefficient in the IEEE standard floating-point number format. The DBNS digital output from ADC is produced through a new double base number encoder (DBNE). The multiplied output is in the format of the IEEE standard floating-point number (FPNS). The proposed circuits process multiplication and conversion together. Compared to a typical multiplier that uses the FPNS, the proposed multiplier also consumes 45% less gates, and 44% faster than the FPNS multiplier on Spartan-3 FPGA board. The design is verified with FIR filter applications.

• IEIE Transactions on Smart Processing and Computing
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• v.5 no.6
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• pp.454-461
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• 2016

A maximum power point tracking (MPPT) system with fast-tracked time and high power efficiency is presented in this paper. The proposed MPPT system uses an unbounded binary search (UBS) algorithm that continuously tracks the maximum power point (MPP) with a binary system to follow the MPP under rapid-weather-change conditions. The proposed algorithm can decide the correct direction of the MPPT system while comparing the previous power point with the present power point. And then, by fixing the MPP until finding the next MPP, there is no oscillation of voltage MPP, which maximizes the overall power efficiency of the photovoltaic module. With these advantages, this proposed UBS is able to detect the MPP more effectively. This MPPT system is based on a boost converter with a micro-control unit to control analog-to-digital converters and pulse width modulation. Analysis of this work and experimental results show that the proposed UBS MPPT provides fast, accurate tracking with no oscillation in situations where weather rapidly changes and shadow is caused by all sorts of things. The tracking time is reduced by 87.3% and 66.1% under dynamic-state and steady-state operation, respectively, as compared with the conventional 7-bit perturb and observe technique.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.1241-1246
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• 2005

This paper described an 8bit, 100Msample/s CMOS D/A converter using a glich-time minimization technique for the high-speed sampling rate of 100MHz level. The proposed DAC was implemented in 0,35um Hynix CMOS technology and adopts a current mode architecture to optimize sampling rate, resolution, chip area. The DAC linear characteristics was similar to the proposed specification the prototype error between DNL and INL is less than ${\pm}0.09LSB$ respectively. Also, fab-out chip was tested, analysed the cause of error operation, and proposed the field considerations for chip test.